公开(公告)号：US10050006B2

公开(公告)日：2018-08-14

申请号：US15483928

申请日：2017-04-10

Applicant: XINTEC INC.

Inventor： Chia-Lun Shen ,  Yi-Ming Chang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/52 ,  H01L21/78

Abstract: A method for forming a chip package is provided. The method includes providing a first substrate and a second substrate. The first substrate is attached onto the second substrate by an adhesive layer. A first opening is formed to penetrate the first substrate and the adhesive layer and separate the first substrate and the adhesive layer into portions. A chip package formed by the method is also provided.

公开(公告)号：US09881959B2

公开(公告)日：2018-01-30

申请号：US14819348

申请日：2015-08-05

Applicant: XINTEC INC.

Inventor： Po-Shen Lin ,  Chia-Sheng Lin ,  Yi-Ming Chang

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14687

Abstract: A method of manufacturing chip package includes providing a semiconductor substrate having at least a photo diode and an interconnection layer. The interconnection layer is disposed on an upper surface of the semiconductor substrate and above the photo diode and electrically connected to the photo diode. At least a redistribution circuit is formed on the interconnection layer. The redistribution circuit is electrically connected to the interconnection layer. A packaging layer is formed on the redistribution circuit. Subsequently, a carrier substrate is attached to the packaging layer. A color filter is formed on a lower surface of the semiconductor substrate. A micro-lens module is formed under the color filter. The carrier substrate is removed.

公开(公告)号：US09711469B2

公开(公告)日：2017-07-18

申请号：US14715445

申请日：2015-05-18

Applicant: XINTEC INC.

Inventor： Geng-Peng Pan ,  Yi-Ming Chang ,  Chia-Sheng Lin

IPC: H01L23/00 ,  H01L21/033 ,  H01L21/302 ,  H01L23/48 ,  H01L21/268 ,  H01L21/48 ,  H01L21/768

CPC classification number: H01L24/03 ,  H01L21/0273 ,  H01L21/0334 ,  H01L21/268 ,  H01L21/302 ,  H01L21/48 ,  H01L21/481 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L2224/0231 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/03831 ,  H01L2224/05017 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05557 ,  H01L2224/0557 ,  H01L2924/00014

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first isolation layer is formed on a first surface of a wafer substrate. A conductive pad is formed on the first isolation layer. A hollow region through the first surface and a second surface of the wafer substrate is formed, such that the first isolation layer is exposed through the hollow region. A laser etching treatment is performed on the first isolation layer that is exposed through the hollow region, such that a first opening is formed in the first isolation layer, and a concave portion exposed through the first opening is formed in the conductive pad.

公开(公告)号：US09611143B2

公开(公告)日：2017-04-04

申请号：US14676738

申请日：2015-04-01

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Sheng Lin ,  Yi-Ming Chang

IPC: H01L21/00 ,  B81C1/00 ,  H01L21/78 ,  H01L23/00 ,  H01L21/683 ,  H01L27/146 ,  B81B7/00 ,  H01L23/544

CPC classification number: B81C1/00896 ,  B81B7/007 ,  B81B2207/096 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L24/11 ,  H01L24/43 ,  H01L24/83 ,  H01L27/14618 ,  H01L27/14687 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2224/0231 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/05032 ,  H01L2924/05432 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for forming a chip package is provided. The method includes providing a substrate and a capping layer, wherein the substrate has a sensing device therein adjacent to a surface of the substrate. The capping layer is attached to the surface of the substrate by an adhesive layer, wherein the adhesive layer covers the sensing device. A dicing process is performed on the substrate, the adhesive layer, and the capping layer along a direction to form individual chip packages.

公开(公告)号：US09236320B2

公开(公告)日：2016-01-12

申请号：US14315163

申请日：2014-06-25

Applicant: XINTEC INC.

Inventor： Yi-Ming Chang ,  Tsang-Yu Liu ,  Yen-Shih Ho ,  Ying-Nan Wen

IPC: H01L23/31 ,  H01L23/00

CPC classification number: H01L23/3171 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06155 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/10157 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip package is provided. The chip package includes a semiconductor chip, an isolation layer, a redistributing metal layer, and at least a bonding pad. The semiconductor chip includes at least one conducting disposed on a surface of the semiconductor chip. The isolation layer is disposed on the surface of the semiconductor chip, wherein the isolation layer has at least one first opening to expose the first conducting pad. The redistributing metal layer is disposed on the isolation layer and has at least a redistributing metal line corresponding to the conducting pad, the redistributing metal line is connected to the first conducting pad through the first opening. The bonding pad is disposed on the isolation layer and one side of the semiconductor chip, wherein the redistributing metal line extends to the bonding pad to electrically connect the conducting pad to the bonding pad.

Abstract translation: 提供芯片封装。 芯片封装包括半导体芯片，隔离层，再分布金属层和至少一个焊盘。 半导体芯片包括设置在半导体芯片的表面上的至少一个导体。 隔离层设置在半导体芯片的表面上，其中隔离层具有至少一个第一开口以暴露第一导电焊盘。 再分配金属层设置在隔离层上，并且至少具有对应于导电焊盘的再分布金属线，再分布金属线通过第一开口连接到第一导电焊盘。 接合焊盘设置在隔离层和半导体芯片的一侧，其中再分布金属线延伸到接合焊盘，以将导电焊盘电连接到接合焊盘。

公开(公告)号：US08993365B2

公开(公告)日：2015-03-31

申请号：US14191348

申请日：2014-02-26

Applicant: Xintec Inc.

Inventor： Yi-Ming Chang ,  Kuo-Hua Liu ,  Yi-Cheng Wang ,  Sheng-Yen Chang

IPC: H01L21/00 ,  H01L31/0203 ,  H01L21/683

CPC classification number: H01L21/6836 ,  H01L21/6835 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/48091 ,  H01L2924/16235 ,  H01L2924/00014

Abstract: A wafer packaging method includes the following steps. A wafer having a plurality of integrated circuit units is provided. A first surface of the wafer opposite to the integrated circuit units is ground. A release layer is formed on a second surface of a light transmissive carrier. An ultraviolet temporary bonding layer is formed on the second surface of the light transmissive carrier or a third surface of the wafer. The ultraviolet temporary bonding layer is used to adhere the second surface of the light transmissive carrier to the third surface of the wafer. The first surface of the wafer is adhered to an ultraviolet tape. A fourth surface of the light transmissive carrier is exposed to ultraviolet to eliminate adhesion force of the ultraviolet temporary bonding layer. The light transmissive carrier and the release layer are removed.

Abstract translation: 晶片封装方法包括以下步骤。 提供具有多个集成电路单元的晶片。 与集成电路单元相对的晶片的第一表面被研磨。 剥离层形成在透光载体的第二表面上。 在透光载体的第二表面或晶片的第三表面上形成紫外线临时粘接层。 紫外线暂时接合层用于将透光载体的第二表面粘附到晶片的第三表面。 晶片的第一表面粘附到紫外线带上。 透光载体的第四表面暴露于紫外线以消除紫外线临时粘合层的粘附力。 去除透光载体和释放层。