公开(公告)号：US12056505B2

公开(公告)日：2024-08-06

申请号：US17862257

申请日：2022-07-11

Applicant: XILINX, INC.

Inventor： Ahmad R. Ansari ,  David P. Schultz

IPC: G06F15/177 ,  G06F9/00 ,  G06F9/24 ,  G06F9/445

CPC classification number: G06F9/44505

Abstract: Embodiments herein describe a distributed configuration system for a configurable device. Instead of relying solely on a central configuration manager to distribute configuration information to various subsystems in the device, the embodiments herein include configuration interface managers (CIM) that are distributed in different regions of the device, whether those regions are in one integrated circuit or include multiple integrated circuits. The embodiments can still use a central configuration manager to distribute configuration information in a device image to the plurality of CIMs, which can then forward the configuration information to their assigned regions.

公开(公告)号：US20230153156A1

公开(公告)日：2023-05-18

申请号：US17455074

申请日：2021-11-16

Applicant: Xilinx, Inc.

Inventor： Karthik Shankar ,  Jaideep Dastidar ,  Ahmad R. Ansari ,  Sagheer Ahmad

IPC: G06F9/50

CPC classification number: G06F9/5027

Abstract: Synchronizing system resources of a multi-socket data processing system can include providing, from a primary System-on-Chip (SOC), a trigger event to a global synchronization circuit. The primary SOC is one of a plurality of SOCS and the trigger event is provided over a first sideband channel. In response to the trigger event, the global synchronization circuit is capable of broadcasting a synchronization event to the plurality of SOCS over a second sideband channel. In response to the synchronization event, the system resource of each SOC of the plurality of SOCS is programmed with a common value. The programming synchronizes the system resources of the plurality of SOCS.

公开(公告)号：US11182110B1

公开(公告)日：2021-11-23

申请号：US16547550

申请日：2019-08-21

Applicant: Xilinx, Inc.

Inventor： Ahmad R. Ansari ,  Sagheer Ahmad

IPC: G06F3/06 ,  H03K19/17728 ,  G11C5/14 ,  G11C7/22 ,  G11C11/4076 ,  G06F5/06 ,  G06F13/16 ,  G06F1/3206 ,  G11C7/24 ,  H03K19/173

Abstract: A memory block circuit can include a plurality of data interfaces, a switch connected to each data interface of the plurality of data interfaces, and a plurality of memory banks each coupled to the switch. Each memory bank can include a memory controller and a random access memory connected to the memory controller. The memory block circuit also includes a control interface and a management controller connected to the control interface and each memory bank of the plurality of memory banks. Each memory bank can be independently controlled by the management controller.

公开(公告)号：US10169177B1

公开(公告)日：2019-01-01

申请号：US15802274

申请日：2017-11-02

Applicant: Xilinx, Inc.

Inventor： Banadappa V Shivaray ,  Pranjal Chauhan ,  Pramod Surathkal ,  Alex S. Warshofsky ,  Tomai Knopp ,  Soumitra Kumar Bhowmick ,  Ahmad R. Ansari

IPC: G06F11/22 ,  G06F17/50 ,  H03K19/003

Abstract: Embodiments herein describe a methodology for performing non-destructive LBIST when booting an integrated circuit (IC). In one embodiment, when powered on, the IC begins the boot process (e.g., a POST) which is then paused to perform LBIST. However, instead of corrupting or destroying the boot mode state of the IC, the LBIST is non-destructive. That is, after LBIST is performed, the booting process can be resumed in the same state as when LBIST began.

公开(公告)号：US09755649B1

公开(公告)日：2017-09-05

申请号：US14617424

申请日：2015-02-09

Applicant: Xilinx, Inc.

Inventor： Richa Singhal ,  Edmond Jordan ,  Ahmad R. Ansari

IPC: H03K19/177

CPC classification number: H03K19/17768

Abstract: A method for protecting an integrated circuit device against security violations includes monitoring a component of the integrated circuit device for security violations. A security violation of the component of the integrated circuit device is then identified. The component of the integrated circuit device is then internally destroyed in response to the identified security violation by providing current to the component beyond a tolerable limit of the component.

公开(公告)号：US09632869B1

公开(公告)日：2017-04-25

申请号：US14848070

申请日：2015-09-08

Applicant: Xilinx, Inc.

Inventor： Ting Lu ,  Nishit Patel ,  Ahmad R. Ansari ,  James J. Murray ,  Sagheer Ahmad

IPC: G06F12/00 ,  G06F13/16 ,  G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1052 ,  G11C29/52 ,  G11C2029/0411

Abstract: In approaches for correction of errors introduced in an interconnect circuit, an ECC proxy circuit is coupled between a first interconnect and the second interconnect, and generates for each of the write transactions from a bus master circuit, a first ECC from and associated with data of the write transaction, and transmits the write transaction and associated first ECC on the second interconnect. The ECC proxy circuit also supplements each of the read transactions from the bus master circuit with a reference to a second ECC associated with data referenced by the read transaction. The ECC proxy circuit transmits the read transaction that references the second ECC on the second interconnect. At least one random access memory (RAM) is coupled to the ECC proxy circuit through the second interconnect. The RAM stores data of each write transaction and the first ECC.

公开(公告)号：US09450569B1

公开(公告)日：2016-09-20

申请号：US14731308

申请日：2015-06-04

Applicant: Xilinx, Inc.

Inventor： Ahmad R. Ansari

IPC: G06F1/04 ,  H03K3/012

CPC classification number: G06F1/14 ,  G06F1/324 ,  Y02D10/126

Abstract: A very low power real-time clock is provided. The real-time clock includes a real-time clock core and a real-time clock controller, both included in an electronic device. The core is powered both when the electronic device is powered on and when it is powered off. When the electronic device is powered off, the core operates on battery power. The controller is powered off when the electronic device is powered off, to save power. The core maintains a tick count and a seconds count. Because the core is powered on even when the electronic device is powered off, the core continues to update the tick count and seconds count even when the electronic device is powered off. The controller provides access, to external components, to the core. By not powering the controller when the electronic device is powered off, non-core functions do not draw power from a battery.

Abstract translation: 提供了一个非常低功耗的实时时钟。 实时时钟包括实时时钟核心和实时时钟控制器，均包含在电子设备中。 当电子设备上电时和断电时，内核都将通电。 当电子设备关闭电源时，内核将以电池供电。 当电子设备关闭电源时，控制器关闭电源，以节省电力。 核心保持滴答计数和秒计数。 因为即使电子设备关闭电源，核心仍然通电，即使电子设备断电，核心也会继续更新刻度计数和秒计数。 控制器提供对外部组件到核心的访问。 当电子设备断电时，不对控制器供电，非核心功能不会从电池中吸取电力。

公开(公告)号：US20160085449A1

公开(公告)日：2016-03-24

申请号：US14493081

申请日：2014-09-22

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel ,  Sagheer Ahmad ,  James J. Murray ,  Nishit Patel ,  Ahmad R. Ansari

IPC: G06F3/06 ,  G06F9/30

CPC classification number: G06F3/0604 ,  G06F3/0655 ,  G06F3/0683 ,  G06F9/3004 ,  G06F13/1657 ,  G06F2003/0697

Abstract: In an example, a circuit to manage memory between a first and second microprocessors each of which is coupled to a control circuit, includes: first and second memory circuits; and a switch circuit coupled to the first and second memory circuits, and memory interfaces of the first and second microprocessors, the switch circuit having a mode signal as input. The switch is configured to selectively operate in one of a first mode or a second mode based on the mode signal such that, in the first mode, the switch circuit couples the first memory circuit to the memory interface of the first microprocessor and the second memory circuit to the memory interface of the second microprocessor and, in the second mode, the switch circuit selectively couples the first or second memory circuits to the memory interface of either the first or second microprocessor.

Abstract translation: 在一个示例中，用于管理第一和第二微处理器之间的存储器的电路，每个微处理器耦合到控制电路，包括：第一和第二存储器电路; 以及耦合到第一和第二存储器电路以及第一和第二微处理器的存储器接口的开关电路，开关电路具有作为输入的模式信号。 开关被配置为基于模式信号选择性地以第一模式或第二模式中的一个模式操作，使得在第一模式中，开关电路将第一存储器电路耦合到第一微处理器和第二存储器的存储器接口 电路连接到第二微处理器的存储器接口，并且在第二模式中，开关电路选择性地将第一或第二存储器电路耦合到第一或第二微处理器的存储器接口。

公开(公告)号：US20160055106A1

公开(公告)日：2016-02-25

申请号：US14464654

申请日：2014-08-20

Applicant: Xilinx, Inc.

Inventor： Ahmad R. Ansari ,  Felix Burton

IPC: G06F13/24

CPC classification number: G06F13/24 ,  G06F9/4812

Abstract: Apparatus and methods for handling inter-processor interrupts (IPIs) in a heterogeneous multiprocessor system are provided. The scalable IPI mechanism provided herein entails minimal logic and can be used for heterogeneous inter-processor communication, such as between application processors, real-time processors, and FPGA accelerators. This mechanism is also low cost, in terms of both logic area and programmable complexity. One example system generally includes a first processor, a second processor being of a different processor type than the first processor, and an IPI circuit. The IPI circuit typically includes a first register associated with the first processor, wherein a first bit in the first register indicates whether the first processor has requested to interrupt the second processor; and a second register associated with the second processor, wherein a second bit in the second register indicates whether the second processor has requested to interrupt the first processor.

Abstract translation: 提供了用于处理异构多处理器系统中的处理器间中断（IPI）的设备和方法。 这里提供的可扩展IPI机制需要最小的逻辑，并且可以用于异构处理器间通信，例如应用处理器，实时处理器和FPGA加速器之间。 这种机制在逻辑区域和可编程复杂性方面也是低成本的。 一个示例系统通常包括第一处理器，与第一处理器不同的处理器类型的第二处理器和IPI电路。 IPI电路通常包括与第一处理器相关联的第一寄存器，其中第一寄存器中的第一位指示第一处理器是否请求中断第二处理器; 以及与第二处理器相关联的第二寄存器，其中第二寄存器中的第二位指示第二处理器是否请求中断第一处理器。

公开(公告)号：US20160048193A1

公开(公告)日：2016-02-18

申请号：US14462492

申请日：2014-08-18

Applicant: XILINX, INC.

Inventor： Sagheer Ahmad ,  Ahmad R. Ansari ,  Soren Brinkmann

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3215 ,  G06F12/1009 ,  G06F12/1027 ,  G06F13/24 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

Abstract: An apparatus is disclosed that includes a processing sub-system having a plurality of processor circuits and an interrupt control circuit. The interrupt control circuit is configured to, in response to a peripheral interrupt, initiate performance of a task indicated by the peripheral interrupt by at least one of the plurality of processor circuits. The processing sub-system is configured to generate a power-down control signal in response to suspension of the plurality of processor circuits. A power management circuit disables power to the processing sub-system, including the interrupt control circuit, in response to the power-down control signal. The power management circuit enables power to the processing sub-system in response to a power-up control signal. The apparatus also includes a proxy interrupt control circuit configured to generate the power-up control signal in response to receiving a peripheral interrupt and power to the processing sub-system being disabled.

Abstract translation: 公开了一种包括具有多个处理器电路和中断控制电路的处理子系统的装置。 中断控制电路被配置为响应于外围中断，由多个处理器电路中的至少一个启动由外设中断指示的任务的执行。 处理子系统被配置为响应于多个处理器电路的暂停而产生掉电控制信号。 功率管理电路响应于掉电控制信号而禁止包括中断控制电路在内的处理子系统的电力。 电源管理电路响应于上电控制信号使处理子系统能够供电。 该设备还包括代理中断控制电路，其配置为响应于接收到外围中断而产生加电控制信号，并且对被禁用的处理子系统的电力。