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109 条记录 (耗时 0.021 秒)

    Sheet sorter and method of controlling the sheet sorter
    11.
    发明授权
    Sheet sorter and method of controlling the sheet sorter 失效
    纸张分拣机和纸张分拣机的控制方法

    公开(公告)号：US6062555A

    公开(公告)日：2000-05-16

    申请号：US61290

    申请日：1998-04-17

    申请人： Takahiro Ono ,  Takeshi Kakinuma ,  Tetsunobu Shibata ,  Nobuyoshi Suzuki ,  Yasuhiro Fujimoto ,  Masahiro Ueda

    发明人： Takahiro Ono ,  Takeshi Kakinuma ,  Tetsunobu Shibata ,  Nobuyoshi Suzuki ,  Yasuhiro Fujimoto ,  Masahiro Ueda

    IPC分类号： B65H31/24 ,  B65H39/11 ,  G03G15/00 ,  B65H33/04 ,  B65H39/02 ,  B65H39/075

    CPC分类号： G03G15/6538 ,  B65H39/11 ,  B65H2408/113

    摘要： A sheet sorter includes an array of a plurality of sorting trays which are mounted on a sorter body and arranged in a vertical direction and a general-purpose tray which is mounted on the sorter body and is larger than each of the sorting trays in capacity so that it accommodates a larger number of sheets than each of the sorting trays. A tray drive mechanism provided in the sorter body moves up and down the sorting trays and the general-purpose tray so that sheets transferred by a transfer mechanism provided in the sorter body are selectively discharged onto the sorting trays or the general-purpose tray. The array of the sorting trays is positioned above the general-purpose tray. The sorting tray array and the general-purpose tray are normally held in a position where the sheet discharge port of the sheet transfer mechanism is positioned between the lowermost tray of the sorting tray array and the general-purpose tray as seen in a vertical direction.

    摘要翻译： 片材分拣机包括安装在分拣机主体上并沿垂直方向布置的多个分拣盘的阵列，以及安装在分拣机主体上并且比每个分拣盘容量大的通用托盘 它比每个分类托盘容纳更多的片材。 设置在分拣机主体中的托盘驱动机构在分拣托盘和通用托盘上上下移动，使得设置在分拣机主体中的传送机构传送的片材被选择性地排放到分拣盘或通用托盘上。 分类托盘的阵列位于通用托盘的上方。 分类托盘阵列和通用托盘通常保持在片材传送机构的片材排出口位于分类托盘阵列的最下面托盘和从垂直方向观察的通用托盘之间的位置。

    Sorter having a pivoting non-sort bin
    12.
    发明授权
    Sorter having a pivoting non-sort bin 失效
    分拣机具有旋转非分拣机

    公开(公告)号：US5407192A

    公开(公告)日：1995-04-18

    申请号：US60933

    申请日：1993-05-13

    申请人： Masahiro Ueda ,  Yasuhiro Fujimoto ,  Terutoshi Nakao

    发明人： Masahiro Ueda ,  Yasuhiro Fujimoto ,  Terutoshi Nakao

    IPC分类号： B65H39/11 ,  B65H39/10

    CPC分类号： B65H39/11 ,  B65H2408/113 ,  B65H2601/251

    摘要： A sorter for sorting sheets successively supplied thereto, comprising: a fixed frame; a movable frame movable vertically with respect to the fixed frame; a plurality of bins arranged one over another at a predetermined distance and each having an upper surface sloping upwardly in a sheet supply direction for receiving thereon one or more of the sheets, the bins being supported on the movable frame; a non-sort bin situated upwardly of the bins and supported pivotally on an upper portion of the movable frame for receiving the non-sorted sheets, the non-sort bin being biased normally so as to slant upwardly in the sheet supply direction; and a holder mounted on the fixed frame, at a position to which the sheets are to be supplied, for holding the non-sorer bin horizontally against the bias.

    摘要翻译： 一种分拣机，用于对连续提供的纸张进行分类，包括：固定框架; 可移动框架，其相对于所述固定框架垂直移动; 以预定距离一个接一个布置的多个箱体，每个箱体具有在片材供给方向上向上倾斜的上表面，用于在其上容纳一个或多个所述片材，所述箱体被支撑在所述可移动框架上; 位于所述箱子上方并且可枢转地支撑在所述可移动框架的上部以用于接收未分选纸张的非分类箱，所述非分类箱正常地偏压以沿所述纸张供给方向向上倾斜; 以及安装在所述固定框架上的待保持所述片材被供应的位置的保持器，用于将所述不干燥箱水平地抵靠所述偏压保持。

    Buffer circuit using capacitors to control the slow rate of a driver transistor
    13.
    发明授权
    Buffer circuit using capacitors to control the slow rate of a driver transistor 失效
    缓冲电路采用电容来控制驱动晶体管的慢速率

    公开(公告)号：US5317206A

    公开(公告)日：1994-05-31

    申请号：US980877

    申请日：1992-11-24

    申请人： Toshiaki Hanibuchi ,  Masahiro Ueda

    发明人： Toshiaki Hanibuchi ,  Masahiro Ueda

    IPC分类号： H03K17/16 ,  H03K5/01 ,  H03K17/567 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/07 ,  H03K5/12

    CPC分类号： H03K19/00361 ,  H03K5/01

    摘要： First and second capacitor circuits responsive to a potential applied to an input node for instantaneously supplying a voltage derived by capacitance division to control electrodes of first and second output MOS transistors which drive an output node. When the output node reaches a predetermined potential level, the control electrode node of the first output transistor or the control electrode node of the second output transistor is driven to ground potential or power supply potential by the MOS transistor responding to a delay signal of an input signal. A smaller buffer circuit which has improved output response and reduced through current is described. The output signal transitioning speed can also be easily altered.

    摘要翻译： 响应于施加到输入节点的电位的第一和第二电容器电路，用于将由电容分压导出的电压瞬时提供给驱动输出节点的第一和第二输出MOS晶体管的控制电极。 当输出节点达到预定电位电平时，第一输出晶体管的控制电极节点或第二输出晶体管的控制电极节点由MOS晶体管响应输入的延迟信号被驱动到地电位或电源电位 信号。 描述了具有改善的输出响应和减小的通过电流的较小的缓冲电路。 输出信号转换速度也可以轻易改变。

    Semiconductor integrated circuit having region for forming complementary field effect transistors and region for forming bipolar transistors
    14.
    发明授权
    Semiconductor integrated circuit having region for forming complementary field effect transistors and region for forming bipolar transistors 失效
    具有用于形成互补场效应晶体管的区域和用于形成双极晶体管的区域的半导体集成电路

    公开(公告)号：US5072285A

    公开(公告)日：1991-12-10

    申请号：US482954

    申请日：1990-02-22

    申请人： Masahiro Ueda ,  Toshiaki Hanibuchi ,  Kimio Ueda

    发明人： Masahiro Ueda ,  Toshiaki Hanibuchi ,  Kimio Ueda

    IPC分类号： H01L21/8249 ,  H01L21/82 ,  H01L27/06 ,  H01L27/118 ,  H03K19/08

    CPC分类号： H01L27/11896

    摘要： A Bi-CMOS gate array comprises basic cells combining CMOS transistors and bipolar transistors. The basic cell is formed of a region for forming p-MOS transistors, a region for forming n-MOS transistors and a region for forming bipolar transistors. The region for forming p-MOS transistors comprises gates aligned spaced apart from each other in a first direction and p-type source and drain regions formed spaced apart from each other in the first direction so as to be disposed at the opposite sides of each gate and having a predetermined width. The region for forming n-MOS transistors comprises gates formed spaced apart from each other in the first direction and n-type source and drain regions formed spaced apart from each other in the first direction so as to be disposed at the opposite sides of each gate and having a predetermined width. The region for forming bipolar transistors comprises p-type source or drain region of the region for forming p-MOS transistors as a base region, and an n-type emitter region formed in the base region and a region for taking out the potential of substrate of the p-MOS transistor as a collector region. An npn bipolar transistor formed in the region for forming p-MOS transistors can be electrically isolated from the other p-MOS transistor and used by holding gates disposed at the opposite sides of the base region at a power supply potential.

    摘要翻译： 双CMOS门阵列包括组合CMOS晶体管和双极晶体管的基本单元。 基本单元由用于形成p-MOS晶体管的区域，用于形成n-MOS晶体管的区域和用于形成双极晶体管的区域形成。 用于形成p-MOS晶体管的区域包括在第一方向上彼此间隔开的栅极和在第一方向上彼此间隔开形成的p型源极和漏极区域，以便设置在每个栅极的相对侧 并具有预定的宽度。 用于形成n-MOS晶体管的区域包括在第一方向上彼此间隔开的栅极和在第一方向上彼此间隔开形成的n型源极和漏极区域，以便设置在每个栅极的相对侧 并具有预定的宽度。 用于形成双极晶体管的区域包括用于形成p-MOS晶体管作为基极区域的区域的p型源极或漏极区域，以及形成在基极区域中的n型发射极区域和用于取出衬底的电位的区域 作为集电极区域的p-MOS晶体管。 在用于形成p-MOS晶体管的区域中形成的npn双极晶体管可以与另一个p-MOS晶体管电隔离，并且通过将栅极设置在基极区域的相对侧处于供电电位来使用。

    Screen for projection
    15.
    发明授权
    Screen for projection 失效
    投影屏幕

    公开(公告)号：US5040870A

    公开(公告)日：1991-08-20

    申请号：US593047

    申请日：1990-10-05

    申请人： Tetsuro Ohno ,  Kazumitsu Kawamura ,  Masahiro Ueda ,  Shinichi Takemura

    发明人： Tetsuro Ohno ,  Kazumitsu Kawamura ,  Masahiro Ueda ,  Shinichi Takemura

    IPC分类号： G02B1/04 ,  G03B21/62

    CPC分类号： G03B21/62 ,  G02B1/04

    摘要： A screen for projection comprising light-controlling or light-scattering film obtained by curinga composition comprising at least two monomers or oligomers which have a polymerizable carbon-carbon double bond and are capable of forming polymers different in refractive index, respectively;a composition comprising a compound having no polymerizable carbon-carbon double bond and at least one monomer or oligomer which has a polymerizable carbon-carbon double bond and is capable of forming a polymer having a refractive index different from that of said compound; ora composition comprising at least one monomer or oligomer which has a plurality of polymerizable carbon-carbon double bonds in the molecule and shows different refractive indexes before and after being polymerized,the curing being conducted by irradiation with light from a rod-like light source or line light source, or parallel rays of light or light from a point light source.When this screen for projection is used, a bright and moire-free picture image can be obtained.

    Semiconductor integrated circuit device having input/output buffer cells each comprising a plurality of transistor regions arranged in a single line
    16.
    发明授权
    Semiconductor integrated circuit device having input/output buffer cells each comprising a plurality of transistor regions arranged in a single line 失效
    具有输入/输出缓冲单元的半导体集成电路器件，每个单元包括排列成一行的多个晶体管区域

    公开(公告)号：US4992845A

    公开(公告)日：1991-02-12

    申请号：US294020

    申请日：1989-01-06

    申请人： Takahiko Arakawa ,  Kazuhiro Sakashita ,  Satoru Kishida ,  Toshiaki Hanibuchi ,  Ichiro Tomioka ,  Masahiro Ueda ,  Yoshihiro Okuno

    发明人： Takahiko Arakawa ,  Kazuhiro Sakashita ,  Satoru Kishida ,  Toshiaki Hanibuchi ,  Ichiro Tomioka ,  Masahiro Ueda ,  Yoshihiro Okuno

    IPC分类号： H01L21/82 ,  H01L27/118

    CPC分类号： H01L27/11898

    摘要： An internal logic gate portion (3) is provided in the central portion of a semiconductor chip (1), input/output buffers (4) are provided to surround the internal logic gate portion (3), and bonding pads (2) are provided in the peripheral portions of the semiconductor chip (1) corresponding to input/output buffer cells (5) in the input/output buffer. Each of the input/output buffer cells (5) comprises an output P-MOS portion (6), an output N-MOS portion (7), an input/logic P-MOS portion (8) and an input/logic N-MOS portion (9), which are respectively arranged in a single line in the direction from the bonding pads (2) to the internal logic gate portion (3). In the above described structure, the size of each of the input/output buffer cells (5) in the pad arranging direction of the bonding pads (2) is decreased, so that the number of input/output pins can be increased according to the decreased use of space in the pad arranging direction required by each input/output buffer cell (5).

    摘要翻译： 在半导体芯片（1）的中央部分设置有内部逻辑门部（3），设置有用于包围内部逻辑门部（3）的输入/输出缓冲器（4），并且提供接合焊盘（2） 在对应于输入/输出缓冲器中的输入/输出缓冲单元（5）的半导体芯片（1）的外围部分中。 每个输入/输出缓冲器单元（5）包括输出P-MOS部分（6），输出N-MOS部分（7），输入/逻辑P-MOS部分（8）和输入/ MOS部分（9），它们在从接合焊盘（2）到内部逻辑门部分（3）的方向上分别布置成单行。 在上述结构中，键合焊盘（2）的焊盘布置方向上的输入/输出缓冲单元（5）中的每一个的尺寸减小，从而可以根据 减少每个输入/输出缓冲单元（5）所需的排列方向的空间的使用。

    Master slice integrated circuit having high and low speed unit cells
    17.
    发明授权
    Master slice integrated circuit having high and low speed unit cells 失效
    具有高速和低速单元的主分片集成电路

    公开(公告)号：US4922136A

    公开(公告)日：1990-05-01

    申请号：US232091

    申请日：1988-08-15

    申请人： Masahiro Ueda

    发明人： Masahiro Ueda

    IPC分类号： H01L21/82 ,  H01L27/118 ,  H03K19/003 ,  H03K19/173

    CPC分类号： H01L27/11801 ,  H03K19/00323 ,  H03K19/1735

    摘要： A semiconductor integrated circuit of the master slice system is formed by arranging internal cell groups of different operating speeds in the form of arrays respectively. The internal cell groups of different operating speeds can be interconnected with each other through internal connecting areas, to reduce power consumption. The structure of each internal cell group can be optimized in accordance with its operating speed, so that the entire formation area is not much increased. Further, the formation ratio of the internal cell groups of different operating speeds is so appropriately set as to improve availability thereof.

    摘要翻译： 主片系统的半导体集成电路通过分别以阵列的形式排列不同的工作速度的内部单元组而形成。 不同工作速度的内部电池组可以通过内部连接区域彼此互连，以降低功耗。 每个内部电池组的结构可以根据其运行速度进行优化，使得整个形成区域不会增加。 此外，不同操作速度的内部电池组的形成比例被适当地设定为提高其可用性。

    Diesel engine fuel control apparatus
    19.
    发明授权
    Diesel engine fuel control apparatus 失效
    柴油发动机燃油控制装置

    公开(公告)号：US4177788A

    公开(公告)日：1979-12-11

    申请号：US935723

    申请日：1978-08-21

    申请人： Yoshiyuki Morita ,  Masami Itou ,  Shigeyoshi Nomura ,  Masahiro Ueda

    发明人： Yoshiyuki Morita ,  Masami Itou ,  Shigeyoshi Nomura ,  Masahiro Ueda

    IPC分类号： F02D41/06 ,  F02B3/06 ,  F02D1/02 ,  F02D1/08 ,  F02D11/10 ,  F02D41/40 ,  F02D31/00 ,  F02D1/00

    CPC分类号： F02D11/10 ,  F02B3/06 ,  F02D2011/103 ,  Y10S123/11

    摘要： A diesel engine fuel control apparatus is disclosed wherein a control unit for controlling the amount of the supply of fuel by a key switch which selectively connects a start position terminal, a normal position terminal and an interruption position terminal to a power supply, includes a control lever position sensing switching means for controlling a fuel injection pump and switchover means which are connected to at least the start position terminal and the normal position terminal, respectively, to control the energization of an actuator of a pump control lever, and a normally closed switching means which is turned off when an exhaust brake is applied is connected between said normal position terminal and one of said switching means.

    摘要翻译： 公开了一种柴油发动机燃料控制装置，其中控制单元用于通过将开始位置端子，正常位置端子和中断位置端子选择性地连接到电源的键开关来控制燃料供给量，包括控制 杠杆位置感测切换装置，用于分别连接至少起动位置端子和法线位置端子的燃料喷射泵和切换装置，以控制泵控制杆的致动器的通电和常闭开关 当在所述正常位置端子和所述开关装置中的一个之间连接施加排气制动器时关闭的装置。