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    High withstand voltage semiconductor device
    11.
    发明授权
    High withstand voltage semiconductor device 失效
    高耐压半导体器件

    公开(公告)号：US5969400A

    公开(公告)日：1999-10-19

    申请号：US614340

    申请日：1996-03-12

    申请人： Takashi Shinohe ,  Yoshihiro Minami ,  Ichiro Omura

    发明人： Takashi Shinohe ,  Yoshihiro Minami ,  Ichiro Omura

    IPC分类号： H01L27/07 ,  H01L29/06 ,  H01L29/08 ,  H01L29/739 ,  H01L29/861 ,  H01L23/58

    CPC分类号： H01L27/0761 ,  H01L29/0615 ,  H01L29/0834 ,  H01L29/7394 ,  H01L29/7395 ,  H01L29/8611 ,  H01L2924/0002

    摘要： A semiconductor device includes a first semiconductor layer of a first conductivity type having first and second main surfaces, a second semiconductor layer of a second conductivity type selectively formed on the first main surface of the first semiconductor layer, the second semiconductor layer including a first region having a relatively high injection efficiency and a second region having a relatively low injection efficiency and the first region being surrounded by the second region, a third semiconductor layer of the first conductivity type formed on the second main surface of the first semiconductor layer, a first electrode selectively formed on the second semiconductor layer of the second conductivity type and connected to at least the first region, and a second electrode formed on the third semiconductor layer of the first conductivity type.

    摘要翻译： 半导体器件包括具有第一和第二主表面的第一导电类型的第一半导体层，选择性地形成在第一半导体层的第一主表面上的第二导电类型的第二半导体层，第二半导体层包括第一区域 具有相对较高的注入效率和具有相对低的注入效率的第二区域，并且第一区域被第二区域包围，形成在第一半导体层的第二主表面上的第一导电类型的第三半导体层，第一 电极选择性地形成在第二导电类型的第二半导体层上并连接到至少第一区域，第二电极形成在第一导电类型的第三半导体层上。

    Semiconductor memory device
    12.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08179710B2

    公开(公告)日：2012-05-15

    申请号：US12730089

    申请日：2010-03-23

    申请人： Yoshihiro Minami

    发明人： Yoshihiro Minami

    IPC分类号： G11C11/22

    CPC分类号： H01L21/84 ,  G11C11/22 ,  G11C11/223 ,  G11C11/5657 ,  G11C2211/562 ,  G11C2211/5648 ,  H01L27/10802 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7841

    摘要： A memory includes memory cells on a semiconductor layer, in which each of the memory cells includes a source layer and a drain layer in the semiconductor layer; an electrically floating body region provided in the semiconductor layer between the source layer and the drain layer and configured to accumulate or discharge electric charges in order to store logical data; a gate dielectric film provided on the body region and comprising a ferroelectric film with polarization characteristics; and a gate electrode provided on the gate dielectric film above the body region, wherein each memory cell stores a plurality of logical data depending on an amount of electric charges accumulated in the body region and on a polarization state of the ferroelectric film.

    摘要翻译： 存储器包括半导体层上的存储单元，其中每个存储单元包括半导体层中的源极层和漏极层; 电浮置体区域，设置在所述源极层和漏极层之间的所述半导体层中，并且被配置为积累或放电电荷以便存储逻辑数据; 设置在所述本体区域上并具有极化特性的铁电体膜的栅极电介质膜; 以及设置在所述体区域上方的所述栅极电介质膜上的栅电极，其中，每个存储单元根据所述体区中累积的电荷量和所述强电介质膜的极化状态来存储多个逻辑数据。

    Semiconductor memory device with cell transistors having electrically floating channel bodies to store data
    13.
    发明授权
    Semiconductor memory device with cell transistors having electrically floating channel bodies to store data 有权
    具有电池晶体管的半导体存储器件具有电浮动通道体以存储数据

    公开(公告)号：US07265419B2

    公开(公告)日：2007-09-04

    申请号：US11041250

    申请日：2005-01-25

    申请人： Yoshihiro Minami

    发明人： Yoshihiro Minami

    IPC分类号： H01L27/01

    CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L29/7841 ,  Y10S257/90

    摘要： A semiconductor memory device includes: a semiconductor device base having an insulating substrate and a semiconductor layer overlying it; a cell array formed on the semiconductor device base with cell transistors disposed in such a manner that each of source and drain layers is shared by adjacent two cell transistors arranged in a direction, the cell transistor having an electrically floating channel body to store data defined by a carrier accumulation state of the channel body; and logic transistors formed on the semiconductor device base to constitute a peripheral circuit of said cell array, wherein at least a part of source and drain layers of each the cell transistor is formed with a thickness different from source and drain layers of the logic transistors.

    摘要翻译： 半导体存储器件包括：半导体器件基底，具有绝缘基底和覆盖其上的半导体层; 形成在半导体器件基底上的单元阵列，其中单元晶体管以这样的方式设置，使得源极和漏极层中的每一个由在一个方向上排列的相邻的两个单元晶体管共享，该单元晶体管具有电浮动沟道体，以存储由 通道体的载体积聚状态; 以及形成在所述半导体器件基底上的逻辑晶体管，以构成所述单元阵列的外围电路，其中每个所述单元晶体管的源极和漏极层的至少一部分形成为具有与所述逻辑晶体管的源极和漏极层不同的厚度。

    Semiconductor device
    20.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20050269642A1

    公开(公告)日：2005-12-08

    申请号：US11015036

    申请日：2004-12-20

    申请人： Yoshihiro Minami

    发明人： Yoshihiro Minami

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/06 ,  H01L27/08 ,  H01L27/088 ,  H01L27/10 ,  H01L27/12 ,  H01L29/786

    CPC分类号： H01L27/0255 ,  H01L27/1203 ,  H01L29/7841 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device comprises a semiconductor substrate; an embedded insulating layer provided on the semiconductor substrate; a semiconductor layer provided on the embedded insulating layer; a transistor including a first conductivity type source layer formed within the semiconductor layer, a first conductivity type drain layer formed in the semiconductor layer, and a channel forming region between the source layer and the drain layer; and an embedded insulating layer protective diode including a second conductivity type first diffusion layer and a first conductivity type second diffusion layer, the first diffusion layer being at the same potential as a semiconductor substrate region immediately below the channel forming region, the second diffusion layer being provided adjacently to the first diffusion layer and electrically connected to at least one of the source layer, the drain layer and the channel forming region.

    摘要翻译： 半导体器件包括半导体衬底; 设置在半导体基板上的嵌入式绝缘层; 设置在所述嵌入绝缘层上的半导体层; 包括形成在所述半导体层内的第一导电类型源极层，形成在所述半导体层中的第一导电类型漏极层和所述源极层与所述漏极层之间的沟道形成区域的晶体管; 以及包括第二导电型第一扩散层和第一导电型第二扩散层的嵌入式绝缘层保护二极管，所述第一扩散层与所述沟道形成区域正下方的半导体衬底区域处于相同的电位，所述第二扩散层为 与第一扩散层相邻并且电连接到源极层，漏极层和沟道形成区域中的至少一个。