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公开(公告)号：US06649478B2
公开(公告)日：2003-11-18
申请号：US10283981
申请日：2002-10-30
IPC分类号： H01L21336
CPC分类号： H01L29/7802 , H01L21/28 , H01L21/28512 , H01L21/304 , H01L29/0657 , H01L29/167 , H01L29/34 , H01L29/41741 , H01L29/456 , H01L29/66712 , H01L2924/0002 , H01L2924/10158 , Y10S148/135 , Y10S438/928 , Y10S438/938 , Y10S438/964 , Y10S438/977 , H01L2924/00
摘要： A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.
摘要翻译： 一种半导体器件，包括包含砷作为杂质的N型半导体衬底，形成在N型半导体衬底的主表面上的第一电极，形成在N型半导体衬底的另一表面上的接地表面，第二 电极，其形成在地表面上并与N型半导体衬底欧姆接触，形成在N型半导体衬底中的半导体元件和在其第一电极和第二电极之间的流动电流。 该器件具有降低的导通电阻。
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公开(公告)号：US5876861A
公开(公告)日：1999-03-02
申请号：US650437
申请日：1996-05-20
申请人： Ichiharu Kondo , Takao Yoneyama , Masami Yamaoka , Osamu Takenaka
发明人： Ichiharu Kondo , Takao Yoneyama , Masami Yamaoka , Osamu Takenaka
IPC分类号： C30B28/12 , C23C14/02 , C23C14/14 , C23C14/16 , C23C14/18 , C23C14/34 , C30B29/02 , H01L21/28 , H01L21/285 , H01L29/45 , B32B15/04
CPC分类号： C23C14/025 , C23C14/16 , C23C14/165 , C23C14/18 , H01L29/456 , Y10T428/12674 , Y10T428/12889 , Y10T428/12944 , Y10T428/26
摘要： Disclosed is a nickel layer formed on a substrate by sputtering, in which nickel layer a percent ratio of an X-ray diffraction peak intensity of the (200) plane of the nickel layer to that of the (111) plane of the nickel layer is not less than 10%. This nickel layer has a reduced stress, and therefore, lessens a bending of a substrate. The nickel layer is formed by a process for sputtering nickel on a substrate, comprising supplying an argon gas into a vacuum chamber, adjusting a pressure of the argon gas in the vacuum chamber to a predetermined value, ionizing the argon gas, bombarding a target containing nickel with the ionized argon gas, to sputter nickel atoms, and depositing the sputtered nickel atoms onto the substrate, wherein the predetermined pressure of the argon gas is not lower than 12 mTorr.
摘要翻译： 公开了通过溅射在基板上形成的镍层，镍层的镍层的（200）面的X射线衍射峰强度与镍层的（111）面的X射线衍射峰强度的百分比为 不低于10％。 该镍层具有减小的应力，因此减小了基板的弯曲。 镍层通过在基板上溅射镍的方法形成，包括将氩气供应到真空室中，将真空室中的氩气压力调节至预定值，电离氩气，轰击含有 镍与电离氩气溅射镍原子，并将溅射的镍原子沉积到衬底上，其中氩气的预定压力不低于12mTorr。
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公开(公告)号：US5798550A
公开(公告)日：1998-08-25
申请号：US469622
申请日：1995-06-06
IPC分类号： H01L21/336 , H01L29/423 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/66719 , H01L29/402 , H01L29/42368 , H01L29/66712 , H01L29/7811 , H01L29/0615 , H01L29/0638 , H01L29/1095
摘要： The present invention involves a vertical type semiconductor device whereby miniaturization and lowered ON resistance of a cell within the device can be achieved without impairing the functioning of the device. The line width of the gate electrode is made smaller to meeting the demand for miniaturization of the cell while the distance between the channel regions which are diffused into the portions below the gate during double diffusion remains virtually equal to that in the device of larger cell size having a low J.sub.FET resistance component. While the width of the gate electrode is set to be smaller, the mask members used during double diffusion are attached to the side walls of the gate electrode, where their width allows the source region to diffuse to the portion under the gate. Accordingly, miniaturization and lowered ON resistance of the cell can be achieved without impairing the functioning of the device.
摘要翻译： 本发明涉及垂直型半导体器件，由此可以实现器件内的电池的小型化和降低的导通电阻，而不会损害器件的功能。 使栅电极的线宽变小以满足电池小型化的需要，而在双扩散期间扩散到栅极下方的沟道区域之间的距离实际上等于在较大单元尺寸的器件中的沟道区域之间的距离 具有低JFET电阻分量。 虽然栅电极的宽度设定得较小，但是在双扩散期间使用的掩模构件附接到栅电极的侧壁，其宽度允许源极区域扩散到栅极下方的部分。 因此，可以实现电池的小型化和降低的导通电阻，而不会损害器件的功能。
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14.发明授权Method of manufacturing a vertical semiconductor device with ground surface providing a reduced ON resistance 失效制造具有提供降低的导通电阻的地面的垂直半导体器件的方法
公开(公告)号：US5663096A
公开(公告)日：1997-09-02
申请号：US473775
申请日：1995-06-06
IPC分类号： H01L21/28 , H01L21/285 , H01L21/304 , H01L21/336 , H01L29/06 , H01L29/167 , H01L29/34 , H01L29/417 , H01L29/45 , H01L29/76 , H01L29/78 , H01L29/94 , H01L31/062 , H01L21/44
CPC分类号： H01L29/66712 , H01L21/28 , H01L21/28512 , H01L21/304 , H01L29/0657 , H01L29/34 , H01L29/41741 , H01L29/7802 , H01L29/167 , H01L29/456 , H01L2924/0002 , H01L2924/10158 , Y10S148/135 , Y10S438/928 , Y10S438/938 , Y10S438/964 , Y10S438/977
摘要： A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.
摘要翻译： 一种半导体器件，包括包含砷作为杂质的N型半导体衬底，形成在N型半导体衬底的主表面上的第一电极，形成在N型半导体衬底的另一表面上的接地表面，第二 电极，其形成在地表面上并与N型半导体衬底欧姆接触，形成在N型半导体衬底中的半导体元件和在其第一电极和第二电极之间的流动电流。 该器件具有降低的导通电阻。
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公开(公告)号：US5596217A
公开(公告)日：1997-01-21
申请号：US407157
申请日：1989-09-14
申请人： Masami Yamaoka , Shoji Toyoshima
发明人： Masami Yamaoka , Shoji Toyoshima
IPC分类号： H01L27/02 , H01L29/739 , H01L29/866
CPC分类号： H01L29/866 , H01L27/0248 , H01L29/7391
摘要： A semiconductor device includes a diode element for protecting a transistor against an overvoltage. A first region of p-type conductivity is formed on an upper surface of an n-type semiconductor substrate in which base and emitter regions of the transistor are formed. A second region of n.sup.+ -type conductivity whose impurity concentration is higher than that of the n-type semiconductor substrate is formed on its upper surface to be spaced apart from the first region. An insulating film is formed to cover the upper surface of the semiconductor substrate. Furthermore, a conductive film is formed to partially overlap the first and second regions through the insulating film. The first region serves as an anode, the second region serves as a cathode, and the conductive film serves as a gate electrode; thus an overvoltage protection diode is obtained.
摘要翻译： 半导体器件包括用于保护晶体管免受过电压的二极管元件。 在形成晶体管的基极和发射极区域的n型半导体衬底的上表面上形成p型导电性的第一区域。 在其上表面上形成杂质浓度高于n型半导体衬底的n +型导电性的第二区域，以与第一区域间隔开。 形成绝缘膜以覆盖半导体衬底的上表面。 此外，形成导电膜以通过绝缘膜部分地重叠第一和第二区域。 第一区域用作阳极，第二区域用作阴极，并且导电膜用作栅电极; 从而得到过电压保护二极管。
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公开(公告)号：US4994880A
公开(公告)日：1991-02-19
申请号：US412552
申请日：1989-09-25
申请人： Naohito Kato , Yoshiyuki Miyase , Tomoatsu Makino , Kasuhiro Yamada , Masami Yamaoka , Takeshi Matsui , Masahiro Yamamoto , Yoshiki Ishida , Tohru Nomura
发明人： Naohito Kato , Yoshiyuki Miyase , Tomoatsu Makino , Kasuhiro Yamada , Masami Yamaoka , Takeshi Matsui , Masahiro Yamamoto , Yoshiki Ishida , Tohru Nomura
IPC分类号： H01L29/72 , H01L29/06 , H01L29/417
CPC分类号： H01L29/0692 , H01L29/41708
摘要： Base regions of first and second stage transistors are formed in a semiconductor substrate consisting of low and high resistivity collector layers, and emitter regions are formed in the respective base regions. The emitter region of the second stage transistor has an interdigital structure with a plurality of finger portions, and an emitter surface electrode is formed on the emitter region of the second stage transistor. The second stage transistor emitter surface electrode has an extending portion at a position spaced apart from a transistor operation region where the finger portions are formed. An emitter connection electrode is formed on the extending portion, and a lead is connected by soldering or the like to the emitter connection electrode. In a portion of the emitter surface electrode extending from the emitter connection electrode to the transistor operation region, slits are formed such that they are bypassed by emitter current so that the lead resistance from each finger portion to the emitter connection electrode is substantially uniform.
摘要翻译： 第一和第二级晶体管的基极区域形成在由低和高电阻率集电极层组成的半导体衬底中，并且发射极区域形成在各个基极区域中。 第二级晶体管的发射极区域具有多个指状部分的叉指结构，并且发射极表面电极形成在第二级晶体管的发射极区域上。 第二级晶体管发射体表面电极在与形成指状部分的晶体管工作区间隔开的位置处具有延伸部分。 发射极连接电极形成在延伸部分上，引线通过焊接等连接到发射极连接电极。 在从发射极连接电极延伸到晶体管工作区域的发射体表面电极的一部分中，形成狭缝，使得它们被发射极电流旁路，使得从每个指状部分到发射极连接电极的引线电阻基本上均匀。
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公开(公告)号：US20050227438A1
公开(公告)日：2005-10-13
申请号：US11140756
申请日：2005-05-31
IPC分类号： H01L21/28 , H01L21/285 , H01L21/304 , H01L21/336 , H01L29/06 , H01L29/167 , H01L29/34 , H01L29/417 , H01L29/45 , H01L29/76 , H01L29/78 , H01L29/94 , H01L31/062
CPC分类号： H01L29/7802 , H01L21/28 , H01L21/28512 , H01L21/304 , H01L29/0657 , H01L29/167 , H01L29/34 , H01L29/41741 , H01L29/456 , H01L29/66712 , H01L2924/0002 , H01L2924/10158 , Y10S148/135 , Y10S438/928 , Y10S438/938 , Y10S438/964 , Y10S438/977 , H01L2924/00
摘要： A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.
摘要翻译： 一种半导体器件，包括包含砷作为杂质的N型半导体衬底，形成在N型半导体衬底的主表面上的第一电极，形成在N型半导体衬底的另一表面上的接地表面，第二 电极，其形成在地表面上并与N型半导体衬底欧姆接触，形成在N型半导体衬底中的半导体元件和在其第一电极和第二电极之间的流动电流。 该器件具有降低的导通电阻。
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18.发明授权Vertical semiconductor device with ground surface providing a reduced ON resistance 失效具有地面的垂直半导体器件提供降低的导通电阻
公开(公告)号：US5689130A
公开(公告)日：1997-11-18
申请号：US409900
申请日：1995-03-22
IPC分类号： H01L21/28 , H01L21/285 , H01L21/304 , H01L21/336 , H01L29/06 , H01L29/167 , H01L29/34 , H01L29/417 , H01L29/45 , H01L29/76 , H01L29/78 , H01L29/94 , H01L31/062 , H01L23/48 , H01L23/52
CPC分类号： H01L29/66712 , H01L21/28 , H01L21/28512 , H01L21/304 , H01L29/0657 , H01L29/34 , H01L29/41741 , H01L29/7802 , H01L29/167 , H01L29/456 , H01L2924/0002 , H01L2924/10158 , Y10S148/135 , Y10S438/928 , Y10S438/938 , Y10S438/964 , Y10S438/977
摘要： A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.
摘要翻译： 一种半导体器件，包括包含砷作为杂质的N型半导体衬底，形成在N型半导体衬底的主表面上的第一电极，形成在N型半导体衬底的另一表面上的接地表面，第二 电极，其形成在地表面上并与N型半导体衬底欧姆接触，形成在N型半导体衬底中的半导体元件和在其第一电极和第二电极之间的流动电流。 该器件具有降低的导通电阻。
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公开(公告)号：US5250449A
公开(公告)日：1993-10-05
申请号：US767313
申请日：1991-09-30
IPC分类号： H01L21/336 , H01L29/10 , H01L29/423 , H01L29/739 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66719 , H01L29/1095 , H01L29/66712 , H01L29/7811 , H01L29/0615 , H01L29/0638 , H01L29/402 , H01L29/42368 , Y10S148/126
摘要： The present invention has as an object the provision of a vertical type semiconductor device whereby miniaturization and lowered ON resistance of the cell can be achieved without impairing the functioning of the device.The line width of the gate electrode is made smaller to meet the demand for miniaturization of the cell, but the distance between the channel regions diffused into the portions below the gate at the time of double diffusion is kept to be virtually equal to that in the device of larger cell size having a low J.sub.FET resistance component. Here, the reason for making the line width of the gate electrode smaller is for securing an area for the source contact.The point is that, while the width of the gate electrode is set to be smaller, the mask members as the mask for double diffusion, having the width allowing the source region to diffuse to the portion under the gate, are attached to the side walls of the gate electrode.Thereby, miniaturization and lowered ON resistance of the cell can be achieved without impairing the functioning of the device.
摘要翻译： 本发明的目的是提供一种垂直型半导体器件，由此可以实现电池的小型化和降低的导通电阻，而不会损害器件的功能。 使栅电极的线宽变小以满足电池小型化的需要，但是扩散到双扩散时的栅极下方的沟道区域之间的距离保持实质上等于 具有低JFET电阻分量的较大单元尺寸的器件。 这里，使栅电极的线宽变小的原因是为了确保源极接触的面积。 要注意的是，尽管栅电极的宽度被设定得较小，但是具有允许源极区域扩散到栅极下方的宽度的双扩散掩模的掩模构件附接到侧壁 的栅电极。 由此，可以实现电池的小型化和降低的导通电阻，而不会损害器件的功能。
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公开(公告)号：US5248623A
公开(公告)日：1993-09-28
申请号：US772472
申请日：1991-10-07
申请人： Hiroshi Muto , Masami Yamaoka
发明人： Hiroshi Muto , Masami Yamaoka
IPC分类号： H01L27/06 , H01L29/861
CPC分类号： H01L27/0688 , H01L29/861 , Y10S148/013
摘要： A diode which includes a first region formed in a polycrystalline silicon layer formed on a substrate. The diode has a predetermined width W and is one of an intrinsic region and a region including impurities at a low concentration therein, a second region and a third region including P-type impurities and N-type impurities therein respectively and both being oppositely arranged from each other with the first region therebetween in the polycrystalline silicon layer. Electrodes are electrically connected to the second region and the third region respectively, and further the film characteristic of the polycrystalline silicon layer and the predetermined width W thereof are determined in such a manner as to fulfill the following equation:W.sub.D .ltoreq.W.ltoreq.LL represents a carrier diffusion length and W.sub.D represents a width of the depletion layer created in the polycrystalline silicon layer when the voltage corresponding to the withstand voltage required by the polycrystalline diode as mentioned above, is applied thereto.
摘要翻译： 一种二极管，其包括形成在形成于基板上的多晶硅层中的第一区域。 二极管具有预定的宽度W，并且是本征区域和包括其中低浓度的杂质的区域中的一个，第二区域和分别包括P型杂质和N型杂质的第三区域，并且两者分别从 在多晶硅层中彼此具有第一区域。 电极分别电连接到第二区域和第三区域，并且进一步确定多晶硅层的膜特性和其预定宽度W，以便满足以下等式：WD
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