Abstract:
An analog image memory device using charge transfer and comprising:a memory zone of N lines of M memory points, each memory point being formed by the integration on the same semiconductor substrate of an MIS capacity separated from a diode by a screen grid,means for selecting each memory point,means for writing in each memory point a charge amount corresponding to the analog signal to be stored andmeans for reading the memory zone line by line after writing.
Abstract:
The present invention concerns an analysis process of a line transfer photosensitive device.The charge-signal and the charge noise transfers from the columns towards the memory have the same duration and are made by using a same training charge, stored in memory, that must be at least sufficient to allow to pass in high inversion at the beginning of the transfer from the columns towards the memory. The transfers of the charge-signal and the charge-noise from the memory towards the read-out register or the drain have the same duration and are made by using training charges at least sufficient to allow to pass in high inversion at the beginning of the transfer. These training charges are read with the charge-signal or collected with the charge-noise.
Abstract:
A device for controlling an image sensor including at least one photosensitive cell including a photodiode capable of discharging into a sense node via a first MOS transistor, the sense node being connected to the gate of a second MOS transistor having its source connected to a processing system. The device includes a bias circuit capable of increasing the voltage of the source during the discharge of the photodiode into the sense node.
Abstract:
An image sensor including photosensitive cells including photodiodes and at least one additional circuit with a significant heat dissipation including transistors. The image sensor is made in monolithic form and includes a layer of a semiconductor material having first and second opposite surfaces and including, on the first surface side, first regions corresponding to the power terminals of the transistors, the lighting of the image sensor being intended to be performed on the second surface side; a stack of insulating layers covering the first surface; a thermally conductive reinforcement covering the stack on the side opposite to the layer; and thermally conductive vias connecting the layer to the reinforcement.
Abstract:
An image sensor including photosensitive cells including photodiodes and at least one additional circuit with a significant heat dissipation including transistors. The image sensor is made in monolithic form and includes a layer of a semiconductor material having first and second opposite surfaces and including, on the first surface side, first regions corresponding to the power terminals of the transistors, the lighting of the image sensor being intended to be performed on the second surface side; a stack of insulating layers covering the first surface; a thermally conductive reinforcement covering the stack on the side opposite to the layer; and thermally conductive vias connecting the layer to the reinforcement.
Abstract:
An image sensor including a pixel assembly, each pixel including a photodiode and an access transistor connected to a read circuit, the photodiode and the access transistor being formed in and above a first semiconductor substrate, all or part of the read circuit being formed in a second semiconductor substrate, the second substrate being placed above the first substrate and separated therefrom by an intermediary insulating layer covering the access transistor, the photodiode receiving incident photons on its lower surface side opposite to the intermediary insulating layer.
Abstract:
A method of detecting electromagnetic radiation imparted onto a matrix of photosensitive photomos networks in which pixels of each photomos network are simultaneously exposed to electromagnetic radiation source for a predetermined period of time. Thereafter, transfer signals are applied to each photomos pixel and accumulated charges corresponding to the strength of the radiation imparted onto the pixels are transferred in a columnwise fashion to the end of each column of the photomos networks. The charges are summed at the end of the columns and placed in a reading register. The charges in the reading register of each photomos network are summed and a signal is output corresponding to the strength of the electromagnetic radiation imparted onto the photomos network.
Abstract:
A CCD shift register having a reading device, or charge/voltage conversion device, at one end. This reading device or charge/voltage conversion device includes a diode, a precharging transistor, and an amplifier with high input impedance. To improve the efficiency of the charge transfer and, more generally, the behavior of the register, especially at high frequencies, it is proposed to shape the final gate of the register, and the diode, in such a way that the width along which the gate is adjacent to the diode (i.e. the width along which the end of the channel is adjacent to the diode) is great while, at the same time, the diode surface area is kept small.
Abstract:
The invention relates to photosensitive semiconductor devices and, more particularly, to linear arrays having several parallel rows of photoconductive points and operating in the integration and charge carry mode. In particular, the object of the invention is to reduce a smearing effect.The device of the invention comprises a photosensitive surface (SP) divided into photosensitive surface elements (SI1 to SMn) placed in rows (L1 to Ln) and in columns (C1 to CM). Each column forms a shift register that ends in a storage space (CS1 to CSM) of a readout register (RL) formed by a shift register of the charge transfer type: readout register (RL) being on same semiconductor substrate (10) as photosensitive surface (SP) the device includes.According to a feature of the invention, the device an intermediate zone (ZI) protected from light used to make a separation distance (DS) between photosensitive surface (SP) and readout register (RL).
Abstract:
A charge transfer memory and its fabrication method are disclosed. The memory has charge transfer shift registers, with four phases and two level of electrodes, and a reading register with two phases and three levels of electrodes. At one end of each shift register, there is a final electrode contiguous with a reading storage electrode of the reading register, which is itself contiguous to a reading transfer electrode. These electrodes are made in a layer, with a second type of doping, of a semiconductor substrate with a first type of doping. Zones with a third type of doping are made facing the transfer electrodes of the reading register. According to the invention, facing the final electrode of each shift register, a zone with a fourth type of doping is made. This zone with a fourth type of doping prevents charges flowing in the reading register from returning to a shift register.