公开(公告)号：US07417268B2

公开(公告)日：2008-08-26

申请号：US11490308

申请日：2006-07-20

Applicant: Yvon Cazaux ,  Didier Herault

Inventor： Yvon Cazaux ,  Didier Herault

IPC: H01L27/148

CPC classification number: H01L27/14609 ,  H01L27/14603 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/1469

Abstract: An image sensor including a pixel assembly, each pixel including a photodiode and an access transistor connected to a read circuit, the photodiode and the access transistor being formed in and above a first semiconductor substrate, all or part of the read circuit being formed in a second semiconductor substrate, the second substrate being placed above the first substrate and separated therefrom by an intermediary insulating layer covering the access transistor, the photodiode receiving incident photons on its lower surface side opposite to the intermediary insulating layer.

Abstract translation: 一种图像传感器，包括像素组件，每个像素包括光电二极管和连接到读取电路的存取晶体管，所述光电二极管和存取晶体管形成在第一半导体衬底中和上方，全部或部分读取电路形成为 第二半导体衬底，第二衬底被放置在第一衬底之上，并通过覆盖存取晶体管的中间绝缘层与其隔开，光电二极管在其与中间绝缘层相对的下表面侧接收入射光子。

公开(公告)号：US20070018075A1

公开(公告)日：2007-01-25

申请号：US11490308

申请日：2006-07-20

Applicant: Yvon Cazaux ,  Didier Herault

Inventor： Yvon Cazaux ,  Didier Herault

IPC: H01L27/00

CPC classification number: H01L27/14609 ,  H01L27/14603 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/1469

Abstract: An image sensor including a pixel assembly, each pixel including a photodiode and an access transistor connected to a read circuit, the photodiode and the access transistor being formed in and above a first semiconductor substrate, all or part of the read circuit being formed in a second semiconductor substrate, the second substrate being placed above the first substrate and separated therefrom by an intermediary insulating layer covering the access transistor, the photodiode receiving incident photons on its lower surface side opposite to the intermediary insulating layer.

Abstract translation: 一种图像传感器，包括像素组件，每个像素包括光电二极管和连接到读取电路的存取晶体管，所述光电二极管和存取晶体管形成在第一半导体衬底中和上方，全部或部分读取电路形成为 第二半导体衬底，第二衬底被放置在第一衬底之上，并通过覆盖存取晶体管的中间绝缘层与其隔开，光电二极管在其与中间绝缘层相对的下表面侧接收入射光子。

公开(公告)号：US4878103A

公开(公告)日：1989-10-31

申请号：US297651

申请日：1989-01-17

Applicant: Yvon Cazaux ,  Didier Herault ,  Yves Thenoz ,  Pierre Blanchard

Inventor： Yvon Cazaux ,  Didier Herault ,  Yves Thenoz ,  Pierre Blanchard

IPC: G11C19/28 ,  G11C27/04 ,  H01L21/339 ,  H01L29/762

CPC classification number: G11C27/04 ,  G11C19/287

Abstract: A charge transfer memory and its fabrication method are disclosed. The memory has charge transfer shift registers, with four phases and two level of electrodes, and a reading register with two phases and three levels of electrodes. At one end of each shift register, there is a final electrode contiguous with a reading storage electrode of the reading register, which is itself contiguous to a reading transfer electrode. These electrodes are made in a layer, with a second type of doping, of a semiconductor substrate with a first type of doping. Zones with a third type of doping are made facing the transfer electrodes of the reading register. According to the invention, facing the final electrode of each shift register, a zone with a fourth type of doping is made. This zone with a fourth type of doping prevents charges flowing in the reading register from returning to a shift register.

Abstract translation: 公开了电荷转移存储器及其制造方法。 存储器具有电荷转移移位寄存器，具有四相和两电平电极，以及具有两相和三电平电平的读取寄存器。 在每个移位寄存器的一端，存在与读取寄存器的读取存储电极相邻的最终电极，其本身与读取转移电极相邻。 这些电极制成具有第一类掺杂的半导体衬底的具有第二类掺杂的层。 具有第三类掺杂的区域面向读取寄存器的转移电极。 根据本发明，面对每个移位寄存器的最终电极，制成具有第四类掺杂的区域。 具有第四类掺杂的区域防止在读取寄存器中流动的电荷返回到移位寄存器。

公开(公告)号：US4873562A

公开(公告)日：1989-10-10

申请号：US287887

申请日：1988-12-21

Applicant: Yvon Cazaux ,  Yves Thenoz ,  Didier Herault ,  Pierre Blanchard

Inventor： Yvon Cazaux ,  Yves Thenoz ,  Didier Herault ,  Pierre Blanchard

IPC: G11C27/04 ,  H01L21/339 ,  H01L29/762 ,  H01L29/768

CPC classification number: H01L29/76841

Abstract: Disclosed are a charge-coupled device with lowering of output potential as well as a method for the fabrication of this device. In a known way, the device comprises, upstream on a semiconducting substrate with a first type of doping (P), a semiconducting layer with a second type of doping (N) and an insulating layer covering the former layer. Pairs of electrodes are formed on the insulating layer. Each pair has a transfer electrode and a storage electrode. Zones with a third type of doping N.sup.+) are made in the layer of a second type (N). A layer with a third type of doping (N.sup.-) is made downstream, in the layer with a second type of doping, and, downstream, there is formed at least one other pair of additional transfer and storage electrodes. A zone with a fourth type of doping (N.sup.--) is made beneath the additional transfer electrode in the layer with a third type of doping (N.sup.-). This pair of additional electrodes and the zone with a fourth type of doping make it possible to obtain the lowering of transfer potential at output.

Abstract translation: 公开了具有降低输出电位的电荷耦合器件以及用于制造该器件的方法。 以已知的方式，器件包括在具有第一类型掺杂（P）的半导体衬底上的上游，具有第二类型掺杂（N）的半导体层和覆盖前一层的绝缘层。 在绝缘层上形成一对电极。 每一对具有转移电极和存储电极。 在第二类型（N）的层中制造具有第三类掺杂N +的区域）。 在具有第二种类型的掺杂的层中，具有第三类掺杂（N-）的层被制成下游，并且在下游形成至少另外一对额外的转移和存储电极。 在具有第三类掺杂（N）的层中，在附加转移电极的下方形成具有第四类掺杂（N-）的区域。 这对附加电极和具有第四类掺杂的区域使得可以获得输出时的转移电位的降低。

公开(公告)号：US07253393B2

公开(公告)日：2007-08-07

申请号：US10820407

申请日：2004-04-08

Applicant: Yvon Cazaux ,  Didier Herault

Inventor： Yvon Cazaux ,  Didier Herault

IPC: H01L31/00 ,  H01L27/00 ,  G01J1/44 ,  H01J40/14 ,  H03F3/08

CPC classification number: H04N5/3597 ,  H04N5/374

Abstract: A method for controlling a photosensitive cell including a photodiode connected to a read node via a MOS transfer transistor, the read node being connected to a source of a reference voltage via a MOS reset transistor, cyclically including a waiting phase at the end of which the photodiode is isolated from the reference voltage; an integration phase during which the voltage of the photodiode varies from a reset voltage to a useful voltage that depends on the lighting; and a phase of reading a voltage representative of the useful voltage, wherein the isolation of the photodiode of the read node at the end of the waiting phase includes the steps of setting the transfer transistor to the on state, the reset transistor being off; turning off the transfer transistor; and setting the reset transistor to the on state.

Abstract translation: 一种用于控制包括经由MOS传输晶体管连接到读节点的光电二极管的感光单元的方法，所述读节点经由MOS复位晶体管连接到参考电压源，周期性地包括等待阶段， 光电二极管与参考电压隔离; 光电二极管的电压从复位电压到取决于照明的有用电压的积分阶段; 以及读取代表有用电压的电压的相位，其中在等待阶段结束时读取节点的光电二极管的隔离包括将传输晶体管设置为导通状态的步骤，复位晶体管截止; 关闭传输晶体管; 并将复位晶体管设置为导通状态。

公开(公告)号：US09880057B2

公开(公告)日：2018-01-30

申请号：US13882944

申请日：2011-11-03

Applicant: Yvon Cazaux ,  Benoit Giffard ,  Xavier Hugon

Inventor： Yvon Cazaux ,  Benoit Giffard ,  Xavier Hugon

IPC: G01J5/08 ,  H01L27/146 ,  H01L27/144

CPC classification number: G01J5/0862 ,  H01L27/144 ,  H01L27/14621 ,  H01L27/14647

Abstract: The detector of visible and near-infrared radiation comprises a near-infrared photosensitive element, a readout circuit for reading the near-infrared photosensitive element, four visible photosensitive elements, one of which being placed facing the near-infrared photosensitive element, and four pigmented resin filters to define a pixel quadruplet. A first pixel, including the near-infrared photosensitive element and one of the visible photosensitive elements, is provided with a resin filter opaque to visible radiation. The three other pixels, respectively including the three other visible photosensitive elements, are respectively provided with filters associated with the three primary colors.

公开(公告)号：US08969773B2

公开(公告)日：2015-03-03

申请号：US13637223

申请日：2011-03-25

Applicant: Arnaud Peizerat ,  Yvon Cazaux ,  Michäel Tchagaspanian

Inventor： Arnaud Peizerat ,  Yvon Cazaux ,  Michäel Tchagaspanian

IPC: H01L27/00 ,  H01L27/146

CPC classification number: H01L27/14634 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14612 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14641 ,  H01L27/14643 ,  H01L27/14689 ,  H01L27/1469

Abstract: An imaging device including: plural pixels each including a photodetector; plural reading circuits associated with the plural photodetectors, each reading circuit including a first MOS transistor charging/discharging a photodetector and a second MOS transistor converting charges to be output by the photodetector into voltage; an electronic processing circuit configured to process the voltages outputted by the reading circuits; a first substrate on which are formed the pixels and the reading circuits, and a second substrate, distinct from the first substrate, on which is formed the electronic processing circuit, the second substrate being linked electrically to the first substrate by an electrical interconnection forming an electrical link between the reading circuits and the electronic processing circuit.

Abstract translation: 一种成像装置，包括：多个像素，每个像素包括光电检测器; 与多个光电检测器相关联的多个读取电路，每个读取电路包括对光电检测器进行充电/放电的第一MOS晶体管和将由光电检测器输出的电荷转换为电压的第二MOS晶体管; 电子处理电路，被配置为处理由所述读取电路输出的电压; 其上形成有像素和读取电路的第一衬底和与第一衬底不同的第二衬底，在其上形成电子处理电路，第二衬底通过电互连电连接到第一衬底，形成 读取电路和电子处理电路之间的电连接。

公开(公告)号：US4760558A

公开(公告)日：1988-07-26

申请号：US742617

申请日：1985-06-07

Applicant: Jean L. Berger ,  Louis Brissot ,  Yvon Cazaux

Inventor： Jean L. Berger ,  Louis Brissot ,  Yvon Cazaux

IPC: G11B20/02 ,  G11C27/04 ,  H01L27/105 ,  H01L27/148 ,  H01L29/78 ,  G11C11/34 ,  H04N3/14 ,  H04N5/335

CPC classification number: H01L27/1057 ,  G11C27/04

Abstract: An analog image memory device using charge transfer and comprising:a memory zone of N lines of M memory points, each memory point being formed by the integration on the same semiconductor substrate of an MIS capacity separated from a diode by a screen grid,means for selecting each memory point,means for writing in each memory point a charge amount corresponding to the analog signal to be stored andmeans for reading the memory zone line by line after writing.

Abstract translation: 一种使用电荷转移的模拟图像存储器件，包括：M个存储点的N行的存储区，每个存储点通过在通过屏幕栅极与二极管分离的MIS容量的相同半导体衬底上的积分形成; 选择每个存储点，用于在每个存储器中写入与要存储的模拟信号相对应的电荷量的装置，以及用于在写入之后逐行读取存储区的装置。

公开(公告)号：US4684993A

公开(公告)日：1987-08-04

申请号：US869133

申请日：1986-05-30

Applicant: Jean-Luc Berger ,  Louis Brissot ,  Yvon Cazaux

Inventor： Jean-Luc Berger ,  Louis Brissot ,  Yvon Cazaux

IPC: H01L27/146 ,  H04N5/359 ,  H04N5/372 ,  H04N3/14

CPC classification number: H01L27/14643 ,  H04N3/1525 ,  H04N3/1568 ,  H04N3/1575

Abstract: The present invention concerns an analysis process of a line transfer photosensitive device.The charge-signal and the charge noise transfers from the columns towards the memory have the same duration and are made by using a same training charge, stored in memory, that must be at least sufficient to allow to pass in high inversion at the beginning of the transfer from the columns towards the memory. The transfers of the charge-signal and the charge-noise from the memory towards the read-out register or the drain have the same duration and are made by using training charges at least sufficient to allow to pass in high inversion at the beginning of the transfer. These training charges are read with the charge-signal or collected with the charge-noise.

Abstract translation: 本发明涉及一种线转印感光装置的分析方法。 从列到存储器的充电信号和充电噪声传输具有相同的持续时间，并且通过使用存储在存储器中的相同训练电荷来进行，其必须至少足以允许在开始时通过高反转 从列转移到记忆体。 电荷信号和充电噪声从存储器向读出寄存器或漏极的传输具有相同的持续时间，并且通过使用训练电荷至少足以允许在开始时的高反转中通过 转让。 这些培训费用是用充电信号读取的或用充电噪声收集的。

公开(公告)号：US09191597B2

公开(公告)日：2015-11-17

申请号：US13605685

申请日：2012-09-06

Applicant: Frédéric Barbier ,  Yvon Cazaux

Inventor： Frédéric Barbier ,  Yvon Cazaux

IPC: H04N3/14 ,  H04N5/3745 ,  H04N5/359

CPC classification number: H04N5/3745 ,  H04N5/3597

Abstract: A device for controlling an image sensor including at least one photosensitive cell including a photodiode capable of discharging into a sense node via a first MOS transistor, the sense node being connected to the gate of a second MOS transistor having its source connected to a processing system. The device includes a bias circuit capable of increasing the voltage of the source during the discharge of the photodiode into the sense node.

Abstract translation: 一种用于控制图像传感器的装置，包括至少一个感光单元，该感光单元包括经由第一MOS晶体管能够放电到感测节点的光电二极管，所述感测节点连接到其源极连接到处理系统的第二MOS晶体管的栅极 。 该器件包括偏置电路，其能够在将光电二极管放电到感测节点期间增加源极的电压。