公开(公告)号：US08410828B2

公开(公告)日：2013-04-02

申请号：US12979886

申请日：2010-12-28

Applicant: Rajeev Jain

Inventor： Rajeev Jain

IPC: H03K3/00

CPC classification number: H03K17/164

Abstract: The invention relates to a driver circuit used to transmit a digital signal from a source device to a destination device. The driver circuit provides a controlled switching time to improve digital signal quality, while reducing electromagnetic interference. In the circuit, a pair of first switches of a first plurality are coupled in parallel between a first current node and respective ones of first and second output terminals. A plurality of pairs of second switches of a second plurality are coupled in parallel between a respective second current node and the first and second output terminals. Timing circuitry applies input signals to the pair of first switches and successive input signals to the pairs of second switches so as to develop a staggered voltage across a load coupled between the first and second output terminals.

Abstract translation: 本发明涉及一种用于将数字信号从源设备传输到目标设备的驱动器电路。 驱动电路提供受控的切换时间，以改善数字信号质量，同时减少电磁干扰。 在该电路中，第一多个的一对第一开关并联在第一电流节点和第一和第二输出端子之间。 多个第二组第二开关对在多个第二电流节点和第一和第二输出端之间并联耦合。 定时电路将输入信号施加到一对第一开关和连续的输入信号到成对的第二开关，以便在耦合在第一和第二输出端子之间的负载上产生交错电压。

公开(公告)号：US08395991B2

公开(公告)日：2013-03-12

申请号：US12559152

申请日：2009-09-14

Applicant: Ravin Sachdeva ,  Sumit Johar ,  Emiliano Mario Piccinelli

Inventor： Ravin Sachdeva ,  Sumit Johar ,  Emiliano Mario Piccinelli

IPC: H04J3/14

CPC classification number: H04N19/521 ,  H04N19/156 ,  H04N19/164 ,  H04N19/176 ,  H04N19/187 ,  H04N19/33 ,  H04N19/40 ,  H04N19/513 ,  H04N19/59 ,  H04N19/61

Abstract: Systems and methods are for implementing a NSV2SV converter that converts a non-scalable video signal to a scalable video signal. In an implementation, a non-scalable video signal encoded in H.264/AVC standard is decoded and segmented into spatial data and motion data. The spatial data is resized into a desired resolution by down-sampling the spatial data. The motion data is also resized in every layer, except in the top layer, of a scalable video coding (SVC) encoder by using an appropriate measure. Further, the motion data is refined based on the resized spatial data in every layer of the SVC encoder. The refined motion data and the down-sampled spatial data are then transformed and entropy encoded in the SVC standard in every layer. The SVC encoded output from every layer is multiplexed to produce a scalable video signal.

Abstract translation: 系统和方法用于实现将不可缩放视频信号转换为可伸缩视频信号的NSV2SV转换器。 在实现中，以H.264 / AVC标准编码的不可缩放视频信号被解码并分割成空间数据和运动数据。 通过对空间数据进行下采样，空间数据被调整为期望的分辨率。 通过使用适当的测量，运动数据也可以在可分级视频编码（SVC）编码器的除了顶层之外的每一层中进行大小调整。 此外，基于SVC编码器的每层中的调整大小的空间数据来精细化运动数据。 然后将精细运动数据和下采样空间数据在SVC标准中进行变换和熵编码。 来自每个层的SVC编码的输出被复用以产生可分级的视频信号。

公开(公告)号：US20130003882A1

公开(公告)日：2013-01-03

申请号：US13241944

申请日：2011-09-23

Applicant: ManoharRaju K.S.V. ,  Hiten ADVANI

Inventor： ManoharRaju K.S.V. ,  Hiten ADVANI

IPC: H04L27/00 ,  H03B1/00

CPC classification number: H02M3/156 ,  H04L25/0272 ,  H04L25/0286 ,  H04L25/03343 ,  H04L25/03878 ,  Y10T307/352 ,  Y10T307/549

Abstract: An embodiment of a pre-emphasis circuit, an embodiment of a method for pre-emphasizing complementary single-ended signals, an embodiment of a transmitter, and an embodiment of a communication system.

Abstract translation: 预加重电路的实施例，用于预加强互补单端信号的方法的实施例，发射机的实施例以及通信系统的实施例。

公开(公告)号：US20130003484A1

公开(公告)日：2013-01-03

申请号：US13172592

申请日：2011-06-29

Applicant: Anuj PARASHAR ,  Marc Vernet

Inventor： Anuj PARASHAR ,  Marc Vernet

IPC: G11C8/00

CPC classification number: G11C8/12 ,  G11C7/18 ,  G11C7/22

Abstract: A memory includes memory cells, data lines, block select lines, and selection circuitry. The data lines provide data to and from the memory cells and may be grouped into blocks. Each block includes data lines. Each of the block select lines is associated with a respective one of the blocks. The selection circuitry is select a block in response to a respective block select line and the memory performs a memory operation using the selected bit line block.

Abstract translation: 存储器包括存储器单元，数据线，块选择线和选择电路。 数据线向存储器单元提供数据并从存储器单元提供数据，并且可以将其分组成块。 每个块包括数据线。 每个块选择线与相应的一个块相关联。 选择电路响应于相应的块选择线选择块，并且存储器使用所选择的位线块执行存储器操作。

公开(公告)号：US20130002213A1

公开(公告)日：2013-01-03

申请号：US13170679

申请日：2011-06-28

Applicant: Rupesh Khare ,  Nitin Bansal

Inventor： Rupesh Khare ,  Nitin Bansal

IPC: G05F1/10

CPC classification number: G05F1/563

Abstract: A regulator structure includes a first differential amplifier having a first input coupled to a reference voltage node. A second differential amplifier has a first input coupled to the output of the first differential amplifier. A third differential amplifier has a first input coupled to the output of the first differential amplifier. A first pmos transistor has its gate coupled to the second differential amplifier output, and its drain coupled to a second input of each of the first and second differential amplifiers. A second pmos transistor has its gate coupled to the third differential amplifier output, and its drain configured to output a regulated voltage which is also a second input of the third differential amplifier. A circuit is configured to replicate the regulated voltage and couple the replicated regulated voltage to the drain of the first pmos transistor.

Abstract translation: 调节器结构包括具有耦合到参考电压节点的第一输入的第一差分放大器。 第二差分放大器具有耦合到第一差分放大器的输出的第一输入。 第三差分放大器具有耦合到第一差分放大器的输出的第一输入。 第一pmos晶体管的栅极耦合到第二差分放大器输出，其漏极耦合到第一和第二差分放大器中的每一个的第二输入端。 第二pmos晶体管的栅极耦合到第三差分放大器输出，其漏极被配置为输出也是第三差分放大器的第二输入的调节电压。 电路被配置为复制经调节的电压并将复制的调节电压耦合到第一pmos晶体管的漏极。

公开(公告)号：US20120326517A1

公开(公告)日：2012-12-27

申请号：US13167250

申请日：2011-06-23

Applicant: Rajesh Narwal ,  Shantanu Goel

Inventor： Rajesh Narwal ,  Shantanu Goel

IPC: H02J1/00

CPC classification number: H02J9/061 ,  G06F1/04 ,  G06F1/26 ,  H02J2009/068 ,  H02M1/14 ,  Y10T307/696

Abstract: A system switches between application of a first supply voltage and a second supply voltage to a load. The second supply voltage is a regulated voltage that is generated from the first supply voltage, or is alternatively generated from a reference voltage, such as bandgap. When the load is supplied from the first supply voltage, the regulated voltage is also generated from the first supply voltage. At or after switching the load to the second supply voltage, the regulated voltage is generated instead from the reference voltage. The load is a clock circuit, such as an oscillator. The controlled switching of the supply voltage for the load in the manner described addresses concerns over introducing errors in the output clock signal when the clock circuit's supply voltage is changed.

Abstract translation: 系统在向负载施加第一电源电压和第二电源电压之间切换。 第二电源电压是从第一电源电压产生的调节电压，或者是替代地从参考电压（例如带隙）产生的。 当从第一电源电压提供负载时，也从第一电源电压产生调节电压。 在将负载切换到第二电源电压之后或之后，产生调节电压而不是参考电压。 负载是时钟电路，例如振荡器。 以所述方式控制负载的电源电压切换解决了当时钟电路的电源电压改变时引入输出时钟信号中的误差的问题。

公开(公告)号：US08314633B2

公开(公告)日：2012-11-20

申请号：US12650092

申请日：2009-12-30

Applicant: Nitin Gupta ,  Tapas Nandy ,  Phalguni Bala ,  Pikul Sarkar

Inventor： Nitin Gupta ,  Tapas Nandy ,  Phalguni Bala ,  Pikul Sarkar

IPC: H03K19/003 ,  H03K19/0175

CPC classification number: H03K19/00361 ,  H03K19/018514

Abstract: Described herein are various principles for operating a transmitter circuit to reduce noise affecting a signal being generated and reducing jitter. In some embodiments, a circuit is operated in a way that switching occurs at or above a bit rate of transmission, such that at least one switch changes state at least for every bit. Operating the circuit in such a way leads to a switching rate that is above a resonant frequency of the circuit and prevents large oscillations and noise from being inserted into the signal and causing communication problems.

Abstract translation: 这里描述了用于操作发射机电路以减少影响正在产生的信号的噪声并减少抖动的各种原理。 在一些实施例中，以使得至少一个开关至少对于每一位进行改变状态的切换发生在等于或高于传输比特率的方式来操作电路。 以这种方式操作电路导致高于电路的谐振频率的开关速率，并且防止大的振荡和噪声被插入到信号中并导致通信问题。

公开(公告)号：US20120287237A1

公开(公告)日：2012-11-15

申请号：US13469873

申请日：2012-05-11

Applicant: Emiliano Mario PICCINELLI ,  Pasqualina FRAGNETO ,  Davide ALIPRANDI ,  Beatrice ROSSI ,  Srijib Narayan MAITI

Inventor： Emiliano Mario PICCINELLI ,  Pasqualina FRAGNETO ,  Davide ALIPRANDI ,  Beatrice ROSSI ,  Srijib Narayan MAITI

IPC: H04N13/00

CPC classification number: H04N19/93 ,  H04N19/184 ,  H04N19/467 ,  H04N19/48 ,  H04N19/597 ,  H04N19/91

Abstract: An embodiment of a method is disclosed for encoding a digital video signal including a first video sequence and a second video sequence jointly forming a stereo-view digital video signal. The method includes: subjecting the first video sequence to discrete cosine transform, quantization and run-length coding to produce a sequence of blocks of non-zero digital levels representative of the first video sequence, subjecting the second video sequence to discrete cosine transform, quantization, run-length coding and variable length coding to produce digital messages representative of the second video sequence, merging the bits of the digital messages into the sequence of blocks of digital levels by substituting the bits of the digital messages for respective Least Significant Bits of e.g. the last digital level in the blocks representative of the first video sequence to produce an encoded digital video signal representative of the first video sequence and the second video sequence.

Abstract translation: 公开了一种用于编码包括共同形成立体视图数字视频信号的第一视频序列和第二视频序列的数字视频信号的方法的实施例。 该方法包括：对第一视频序列进行离散余弦变换，量化和游程编码以产生表示第一视频序列的非零数字电平的块序列，对第二视频序列进行离散余弦变换，量化 运行长度编码和可变长度编码以产生表示第二视频序列的数字消息，通过将数字消息的比特代替例如数字消息的相应的最低有效位来将数字消息的比特合并为数字级的块序列 代表第一视频序列的块中的最后数字电平，以产生表示第一视频序列和第二视频序列的编码数字视频信号。

公开(公告)号：US08286012B2

公开(公告)日：2012-10-09

申请号：US13096125

申请日：2011-04-28

Applicant: Satinder Singh Malhi ,  Arant Agrawal

Inventor： Satinder Singh Malhi ,  Arant Agrawal

IPC: G06F1/00 ,  G06F1/26

CPC classification number: G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

Abstract: The present invention provides a method and system for controlling leakage power consumption at a System on Chip (SoC) level during a normal run or a boot-up mode. The leakage power reduction is achieved by incorporating a central programmable controller in the SoC architecture and test structures of idle SoC peripherals to place them into an Absolute Minimum Power consumption state with respect to static and dynamic power.

Abstract translation: 本发明提供一种用于在正常运行或启动模式期间控制片上系统（SoC）级别的泄漏功率消耗的方法和系统。 通过在SoC架构中集成中央可编程控制器和空闲SoC外设的测试结构将其置于相对于静态和动态功率的绝对最小功耗状态下，实现了泄漏功率的降低。

公开(公告)号：US20120198291A1

公开(公告)日：2012-08-02

申请号：US13361749

申请日：2012-01-30

Applicant: Prashant Dubey ,  Akhil Garg ,  Sravan Kumar Bhaskarani

Inventor： Prashant Dubey ,  Akhil Garg ,  Sravan Kumar Bhaskarani

IPC: G11C29/12 ,  G06F11/27

CPC classification number: G11C29/16 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/32 ,  G11C2029/0401 ,  G11C2029/2602 ,  G11C2029/5602

Abstract: A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories. The present disclosure further provides a programmable shared built in self testing (BIST) architecture utilizing globally asynchronous and locally synchronous (GALS) methodology for testing multiple memories. The built in self test (BIST) architecture includes a programmable master controller, multiple memory wrappers, and an interface. The interface can be a globally asynchronous and locally synchronous (GALS) interface.

Abstract translation: 一种共享用于多个嵌入式存储器的测试组件的系统和方法以及包含其的存储器系统。 存储系统包括多个测试控制器，多个接口设备，主控制器和串行接口。 主控制器用于使用串行接口和本地测试控制器初始化每个不同内存组的测试。 存储器系统导致路由拥塞减少和多个不同存储器的更快测试。 本公开还提供了一种使用全局异步和本地同步（GALS）方法来测试多个存储器的可编程共享内建自测试（BIST）架构。 内置自检（BIST）架构包括可编程主控制器，多个存储器包装器和接口。 该接口可以是全局异步和本地同步（GALS）接口。