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35491 条记录 (耗时 0.061 秒)

    Methods and apparatus to balance propagation delay and bus emissions in transceivers
    11.
    发明授权
    Methods and apparatus to balance propagation delay and bus emissions in transceivers 有权

    公开(公告)号：US12132481B2

    公开(公告)日：2024-10-29

    申请号：US17709734

    申请日：2022-03-31

    申请人： Texas Instruments Incorporated

    发明人： Lokesh Kumar Gupta ,  Upasana Bhattacharya

    IPC分类号： H03K19/0948 ,  H03K3/0233 ,  H04L12/40

    CPC分类号： H03K19/0948 ,  H03K3/02337 ,  H04L12/4013 ,  H04L2012/40215

    摘要： Methods, apparatus, systems, and articles of manufacture are disclosed to buffer an input voltage. An example apparatus includes first inverter circuitry to invert the input voltage and produce a first inverted voltage; second inverter circuitry coupled to the first inverter circuitry, the second inverter circuitry to invert the first inverted voltage and produce a second inverted voltage at a rate based on a first current controlled transistor; third inverter circuitry coupled to the second inverter circuitry, the third inverter circuitry to invert the second inverted voltage and produce a third inverted voltage at a rate based on a second current controlled transistor; and fourth inverter circuitry coupled to the third inverter circuitry, the fourth inverter circuitry to invert the third inverted voltage and produce an output voltage, wherein the output voltage matches the input voltage.

    LOW LATENCY SERIAL BUS
    15.
    发明公开
    LOW LATENCY SERIAL BUS 审中-公开

    公开(公告)号：US20240356774A1

    公开(公告)日：2024-10-24

    申请号：US18240827

    申请日：2023-08-31

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Win Naing MAUNG ,  Roy WOJCIECHOWSKI ,  James SKIDMORE

    IPC分类号： H04L12/40

    CPC分类号： H04L12/40058 ,  H04L12/40013 ,  H04L12/40071 ,  H04L12/40117

    摘要： A serial bus control circuit includes a link layer control circuit. The link layer control circuit is configured to control isochronous data transfer over a serial bus. The link layer control circuit includes an isochronous cycle timer configured to provide a cycle frame that is less than 125 microseconds in duration. The link layer control circuit can be configured to set the isochronous cycle timer to provide a cycle frame duration that produces an isochronous transfer latency of no more than 50 microseconds.

    ON-THE-FLY PADDING FOR CNN FEATURE MAPS
    16.
    发明公开
    ON-THE-FLY PADDING FOR CNN FEATURE MAPS 审中-公开

    公开(公告)号：US20240354003A1

    公开(公告)日：2024-10-24

    申请号：US18305871

    申请日：2023-04-24

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Asheesh Bhardwaj ,  William Leven ,  Varun Tripathi

    IPC分类号： G06F3/06 ,  G06N3/0464

    CPC分类号： G06F3/0608 ,  G06F3/0646 ,  G06F3/0673 ,  G06N3/0464

    摘要： Disclosed herein are systems and methods for providing on-the-fly padding to feature maps of convolutional neural networks (CNNs). In an implementation, a processor first identifies a padding schema for a feature map based on a type of convolution to be performed on the feature map. Next the processor identifies a feature vector from the feature map currently in an associated memory. Then, the processor determines a padding for the feature vector based on the padding schema. Finally, the processor applies the padding to the feature vector while the feature vector is transferred from the associated memory to registers of the suitable computer.

    Fault detection in a real-time image pipeline
    18.
    发明授权
    Fault detection in a real-time image pipeline 有权

    公开(公告)号：US12125122B2

    公开(公告)日：2024-10-22

    申请号：US17556161

    申请日：2021-12-20

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Mihir Narendra Mody ,  Niraj Nandan ,  Ankur Ankur ,  Mayank Mangla ,  Prithvi Shankar Yeyyadi Anantha

    IPC分类号： G06T1/20 ,  G06F9/48 ,  G06F11/10 ,  G06T1/60

    CPC分类号： G06T1/20 ,  G06F9/4812 ,  G06F11/1004 ,  G06T1/60

    摘要： A technique including receiving an image stream for processing; processing the received image stream in a real time mode of operation; outputting an indication that an image processing pipeline has begun processing the received image stream; receiving, in response to the indication, first configuration information associated with test data for testing the image processing pipeline; switching the image processing pipeline to a non-real time mode of operation to process the test data based on the first configuration information during a vertical blanking period of the received image stream; loading the test data from an external memory; switching an input of the image processing pipeline from the image stream to the test data; determining a checksum based on the processed test data; comparing the determined checksum to an expected checksum to determine that the test data was successfully processed; and outputting an indication that the test data was successfully processed.

    Partial bit filter for usb interface
    19.
    发明授权
    Partial bit filter for usb interface 有权

    公开(公告)号：US12124390B2

    公开(公告)日：2024-10-22

    申请号：US17680697

    申请日：2022-02-25

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Win N. Maung ,  Suzanne M. Vining ,  Julie Nirchi

    IPC分类号： G06F13/38 ,  G06F13/42

    CPC分类号： G06F13/382 ,  G06F13/4282 ,  G06F2213/0042

    摘要： Data communication devices, e.g., eUSB2 repeaters, include a partial bit filter to filter out a partial bit so it is not transmitted. The partial bit filter includes state-detection-and-hold circuitry having first and second differential signal inputs, a first output and a second output; logic circuitry having a first input coupled to the first output of the state-detection-and hold circuitry, and a second input coupled to the second output of the state-detection-and hold circuitry; and filter circuitry coupled to the logic circuitry and having a control output. The filter circuitry may be implemented as a latch or a network of flip flops. The output control signal of the partial bit filter may be applied to a transmitter in an eUSB2 repeater or to a pass-gate at the output of the transmitter.