公开(公告)号：US20240321758A1

公开(公告)日：2024-09-26

申请号：US18189299

申请日：2023-03-24

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Min-Yu Chen ,  Po-Chen Lai ,  Ming-Chih Yew ,  Shin-Puu Jeng

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H10B80/00

CPC分类号： H01L23/5386 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/5385 ,  H01L24/16 ,  H01L25/0655 ,  H10B80/00 ,  H01L21/6835 ,  H01L23/49833 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2221/68345 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125

摘要： A composite interposer includes a local-silicon-interconnect-containing (LSI-containing) interposer that includes a local silicon interconnect (LSI) bridge; and an organic interposer located on the LSI-containing interposer, including redistribution dielectric layers embedding redistribution wiring interconnects and a metallic counter-deformation structure. The metallic counter-deformation structure includes a plurality of metallic via structures; a first metallic plate located on a first side of the plurality of metallic via structures; and a second metallic plate located on a second side of the plurality metallic via structures and vertically spaced from the first metallic plate.

公开(公告)号：US20240321654A1

公开(公告)日：2024-09-26

申请号：US18734669

申请日：2024-06-05

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jen-Yuan Chang ,  Chien-Chang Lee ,  Chia-Ping Lai

IPC分类号： H01L23/10 ,  H01L23/522 ,  H01L23/535 ,  H01L23/538 ,  H01L23/60 ,  H01L27/06

CPC分类号： H01L23/10 ,  H01L23/5226 ,  H01L23/535 ,  H01L23/5383 ,  H01L23/60 ,  H01L27/0688 ,  H01L23/5225

摘要： A three-dimensional device structure includes a first die, a second die disposed on the first die, and a connection circuit. The first die includes a first semiconductor substrate, a first interconnect structure disposed on the first semiconductor substrate, and a first seal ring surrounding the interconnect structure. The second die includes a second semiconductor substrate, a second interconnect structure disposed on the second semiconductor substrate, and a second seal ring surrounding the interconnect structure. The first connection circuit electrically couples the first seal ring to the second seal ring to provide an electrostatic discharge path.

公开(公告)号：US12100730B2

公开(公告)日：2024-09-24

申请号：US18501396

申请日：2023-11-03

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Po-Chia Lai ,  Stefan Rusu ,  Chun-Yen Lee

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L27/08 ,  H01L49/02

CPC分类号： H01L28/60 ,  H01L21/76838 ,  H01L23/5223 ,  H01L23/5226 ,  H01L27/0805

摘要： Integrated circuit (IC) devices include a metal-insulator-metal (MIM) capacitor having a top electrode plate, a bottom electrode plate, and a plurality of intermediate electrode plates between the top electrode plate and the bottom electrode plate. A plurality of dielectric layers may separate each of the electrode plates of the MIM capacitor from adjacent plates of the MIM capacitor. Each of the intermediate electrode plates may have a thickness that is greater than a thickness of the top electrode plate and the bottom electrode plate. By providing multiple intermediate electrode plates between the top and bottom electrode plates of the MIM capacitor, and allocating the greatest plate thicknesses to the intermediate plates, the capacitance density may be increased in a given area of the IC device, which may provide increased performance for the IC device.

公开(公告)号：US20240312931A1

公开(公告)日：2024-09-19

申请号：US18669577

申请日：2024-05-21

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jen-Yuan CHANG ,  Chien-Chang LEE ,  Chia-Ping LAI

IPC分类号： H01L23/58 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L23/585 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5222 ,  H01L25/0657 ,  H01L23/562 ,  H01L25/18 ,  H01L2225/06544

摘要： A die includes: a semiconductor substrate; an interconnect structure disposed on the semiconductor substrate and including: inter-metal dielectric (IMD) layers; metal features embedded in the IMD layers; and a guard ring structure including concentric first and second guard rings that extend through at least a subset of the IMD layers; and a through silicon via (TSV) structure extending through the semiconductor substrate and the subset of IMD layers to electrically contact one of the metal features. The first guard ring surrounds the TSV structure; and the second guard ring surrounds the first guard ring and is configured to reduce a parasitic capacitance between the guard ring structure and the TSV structure.

公开(公告)号：US12094925B1

公开(公告)日：2024-09-17

申请号：US18229139

申请日：2023-08-01

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jen-Yuan Chang ,  Chien-Chang Lee ,  Chia-Ping Lai ,  Tzu-Chung Tsai

IPC分类号： H01L49/02 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L28/91 ,  H01L21/56 ,  H01L24/80 ,  H01L2224/80895 ,  H01L2224/80896

摘要： A three-dimensional device structure includes a first die including a first semiconductor substrate, a second die disposed on the first die and including a second semiconductor substrate, a dielectric encapsulation (DE) layer disposed on the first die and surrounding the second die, a redistribution layer structure disposed on the second die and the DE layer, and an integrated passive device (IPD) embedded in the DE layer and electrically connected to the first die and the redistribution layer structure.

公开(公告)号：US12088940B2

公开(公告)日：2024-09-10

申请号：US18217794

申请日：2023-07-03

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Yun-Wei Cheng ,  Chia Chun-Wei ,  Chun-Hao Chou ,  Kuo-Cheng Lee

IPC分类号： H04N25/75 ,  H04N25/50

CPC分类号： H04N25/75 ,  H04N25/50

摘要： An image sensor includes a photosensitive sensor, a floating diffusion node, a reset transistor, and a source follower transistor. The reset transistor comprises a first source/drain coupled to the floating diffusion node and a second source/drain coupled to a first voltage source. The source follower transistor comprises a gate coupled to the floating diffusion node and a first source/drain coupled to the second source/drain of the reset transistor. A first elongated contact contacts the second source/drain of the reset transistor and the first source/drain of the source follower transistor. The first elongated contact has a first dimension in a horizontal cross-section and a second dimension in the horizontal cross-section. The second dimension is perpendicular to the first dimension, and the second dimension is less than the first dimension.

公开(公告)号：US20240297087A1

公开(公告)日：2024-09-05

申请号：US18115840

申请日：2023-03-01

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Sheng-Kai CHANG ,  Chih-Kang Han ,  Leo Li ,  Lieh-Chuan Chen ,  Chien-Li Kuo

IPC分类号： H01L23/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC分类号： H01L23/16 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5386 ,  H01L25/0655 ,  H01L21/563 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/1011

摘要： A package module includes an interposer, a plurality of semiconductor dies on the interposer, a module stiffener on the interposer adjacent to the plurality of semiconductor dies, and a molding material layer on the interposer around the plurality of semiconductor dies and the module stiffener.

公开(公告)号：US20240296890A1

公开(公告)日：2024-09-05

申请号：US18662709

申请日：2024-05-13

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chen-Ming Huang ,  Wen-Tuo Huang ,  Yu-Hsiang Yang ,  Yu-Ling Hsu ,  Wei-Lin Chang ,  Chia-Sheng Lin ,  ShihKuang Yang ,  Yu-Chun Chang ,  Hung-Ling Shih ,  Po-Wei Liu ,  Shih-Hsien Chen

IPC分类号： G11C16/10 ,  G11C16/04 ,  H01L29/66 ,  H01L29/78 ,  H10B41/35

CPC分类号： G11C16/10 ,  H01L29/6656 ,  H01L29/7841 ,  H10B41/35 ,  G11C16/04

摘要： A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

公开(公告)号：US12080594B2

公开(公告)日：2024-09-03

申请号：US17872144

申请日：2022-07-25

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Cheng-Lun Tsai ,  Huei-Wen Hsieh ,  Chun-Sheng Chen ,  Kai-Shiang Kuo ,  Jen-Wei Liu ,  Cheng-Hui Weng ,  Chun-Chieh Lin ,  Hung-Wen Su

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76846 ,  H01L21/76862 ,  H01L21/76877 ,  H01L23/53238

摘要： An opening is formed through a dielectric material layer to physically expose a top surface of a conductive material portion in, or over, a substrate. A metallic nitride liner is formed on a sidewall of the opening and on the top surface of the conductive material portion. A metallic adhesion layer including an alloy of copper and at least one transition metal that is not copper is formed on an inner sidewall of the metallic nitride liner. A copper fill material portion may be formed on an inner sidewall of the metallic adhesion layer. The metallic adhesion layer is thermally stable, and remains free of holes during subsequent thermal processes, which may include reflow of the copper fill material portion. An additional copper fill material portion may be optionally deposited after a reflow process.

公开(公告)号：US12075633B2

公开(公告)日：2024-08-27

申请号：US18317958

申请日：2023-05-16

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Yong-Jie Wu ,  Yen-Chung Ho ,  Mauricio Manfrini ,  Chung-Te Lin ,  Pin-Cheng Hsu

IPC分类号： H10B63/00 ,  H01L29/66 ,  H01L29/786 ,  H10B53/30 ,  H10B53/40 ,  H10N70/00 ,  H10N70/20

CPC分类号： H10B63/34 ,  H01L29/66969 ,  H01L29/78642 ,  H01L29/7869 ,  H10B53/30 ,  H10B53/40 ,  H10B63/80 ,  H10N70/011 ,  H10N70/231 ,  H10N70/24

摘要： A device structure includes at least one selector device. Each selector device includes a vertical stack including, from bottom to top, a bottom electrode, a metal oxide semiconductor channel layer, and a top electrode and located over a substrate, a gate dielectric layer contacting sidewalls of the bottom electrode, the metal oxide semiconductor channel layer, and the top electrode, and a gate electrode formed within the gate dielectric layer and having a top surface that is coplanar with a top surface of the top electrode. Each top electrode or each bottom electrode of the at least one selector device may be contacted by a respective nonvolatile memory element to provide a one-selector one-resistor memory cell.