公开(公告)号：US20240105834A1

公开(公告)日：2024-03-28

申请号：US18466322

申请日：2023-09-13

申请人： ROHM CO., LTD.

发明人： Hajime OKUDA ,  Yoshinori FUKUDA ,  Adrian JOITA ,  Toru TAKUMA

IPC分类号： H01L29/78 ,  H01L27/06 ,  H01L29/06 ,  H01L29/423

CPC分类号： H01L29/7813 ,  H01L27/0629 ,  H01L29/0607 ,  H01L29/42368 ,  H01L29/42376

摘要： A semiconductor device includes: a semiconductor region of a first conductivity type having a main surface; a capacitor region of a second conductivity type formed in a surface layer portion of the main surface; and at least one trench structure including a trench formed in the main surface to penetrate the capacitor region, an insulating film covering a wall surface of the trench, and embedded electrodes embedded in the trench so as to form capacitive coupling with the capacitor region through the insulating film.

公开(公告)号：US11923365B2

公开(公告)日：2024-03-05

申请号：US17387178

申请日：2021-07-28

申请人： Samsung Electronics Co., Ltd.

发明人： Jeonghyuk Yim ,  Ki-Il Kim ,  Gil Hwan Son ,  Kang Ill Seo

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L27/0922 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823871 ,  H01L29/0665 ,  H01L29/401 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78645

摘要： Integrated circuit devices may include two transistor stacks including lower transistors having different threshold voltages and upper transistors having different threshold voltages. Gate insulators of the lower transistors may have different dipole elements or different areal densities of dipole elements, and the upper transistors may have different gate electrode structures.

公开(公告)号：US20240063280A1

公开(公告)日：2024-02-22

申请号：US18230423

申请日：2023-08-04

申请人： STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

发明人： Franck JULIEN ,  Julien DELALLEAU ,  Julien DURA ,  Julien AMOUROUX ,  Stephane MONFRAY

IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L29/40

CPC分类号： H01L29/42376 ,  H01L29/7833 ,  H01L29/42368 ,  H01L29/401

摘要： A MOSFET transistor includes, on a semiconductor layer, a stack of a gate insulator and of a gate region on the gate insulator. The gate region has a first gate portion and a second gate portion between the first gate portion and the gate insulator. The first gate portion has a first length in a first lateral direction of the transistor. The second gate portion has a second length in the first lateral direction that is shorter than the first length.

公开(公告)号：US20240063279A1

公开(公告)日：2024-02-22

申请号：US18496336

申请日：2023-10-27

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Doosan Back ,  Dongoh Kim ,  Gyuhyun Kil ,  Jung-Hoon Han

IPC分类号： H01L29/423 ,  H01L29/417 ,  H01L29/51

CPC分类号： H01L29/42368 ,  H01L29/41725 ,  H01L29/513

摘要： A semiconductor device includes a gate stack including a gate insulating layer and a gate electrode on the gate insulating layer. The gate insulating layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer. The semiconductor device also includes a first spacer on a side surface of the gate stack, and a second spacer on the first spacer, wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer, and a dielectric constant of the second spacer is greater than the dielectric constant of the first dielectric layer and less than a dielectric constant of the first spacer.

公开(公告)号：US11908916B2

公开(公告)日：2024-02-20

申请号：US17245853

申请日：2021-04-30

申请人： SK hynix system ic Inc.

发明人： Soon Yeol Park ,  Yoon Hyung Kim ,  Yu Shin Ryu

IPC分类号： H01L29/49 ,  H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3215 ,  H01L29/423

CPC分类号： H01L29/4983 ,  H01L21/28035 ,  H01L21/32155 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/66681 ,  H01L29/7816

摘要： A high voltage semiconductor device includes a semiconductor region of a first conductivity type having a first region and a second region, a first insulation pattern disposed over the first region of the semiconductor region to have a first thickness, a second insulation pattern disposed over the second region of the semiconductor region to have a second thickness greater than the first thickness, and a gate electrode disposed over the first and second insulation patterns to have a step structure over a boundary region between the first and second regions. The gate electrode has a doping profile that a position of a maximum projection range of impurity ions distributed in the gate electrode over the first region is located at substantially the same level as a position of a maximum projection range of impurity ions distributed in the gate electrode over the second region.

公开(公告)号：US20240047573A1

公开(公告)日：2024-02-08

申请号：US18487505

申请日：2023-10-16

申请人： Infineon Technologies Austria AG

发明人： Stefan Tegen ,  Matthias Kroenke

IPC分类号： H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423 ,  H01L29/739

CPC分类号： H01L29/7813 ,  H01L29/401 ,  H01L29/402 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/66666 ,  H01L29/4236 ,  H01L29/42356 ,  H01L29/7827 ,  H01L29/407 ,  H01L29/404 ,  H01L29/7397 ,  H01L29/66348 ,  H01L29/42368

摘要： A transistor device includes a semiconductor substrate having a first major surface, a cell field and an edge termination region laterally surrounding the cell field. The cell field includes: elongate active trenches that extend from the first major surface into the semiconductor substrate, a field plate and a gate electrode being positioned in each elongate active trench, the gate electrode being arranged above and electrically insulated from the field plate; and elongate mesas, each elongate mesa being formed between neighbouring elongate active trenches, the elongate mesas comprising a drift region, a body region on the drift region and a source region on the body region.

公开(公告)号：US11888060B2

公开(公告)日：2024-01-30

申请号：US17446672

申请日：2021-09-01

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Prasad Venkatraman

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66712

摘要： A MOSFET device die includes an active area formed on a semiconductor substrate. The active area includes a first active area portion and a second active area portion. At least one mesa is formed in the semiconductor substrate extending in a longitudinal direction through the active area. The at least one mesa includes a channel region extending in a longitudinal direction. The channel region includes low threshold voltage channel portions and high threshold voltage channel portions. The first active area portion includes the channel portions in a first ratio of low threshold voltage channel portions to high threshold voltage channel portions, and the second active area portion includes channel portions in a second ratio of low threshold voltage channel portions to high threshold voltage channel portions. The first ratio is larger than the second ratio.

公开(公告)号：US11862702B2

公开(公告)日：2024-01-02

申请号：US17727603

申请日：2022-04-22

申请人： Intel Corporation

发明人： Aaron D. Lilak ,  Rishabh Mehandru ,  Cory Weber ,  Willy Rachmady ,  Varun Mishra

IPC分类号： H01L29/423 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L21/8234

CPC分类号： H01L29/42392 ,  H01L21/0217 ,  H01L21/02293 ,  H01L21/02532 ,  H01L21/823431 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1091 ,  H01L29/165 ,  H01L29/42368 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7848 ,  H01L29/78696

摘要： Gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. For example, an integrated circuit structure includes an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin.

公开(公告)号：US20230402082A1

公开(公告)日：2023-12-14

申请号：US18235955

申请日：2023-08-21

申请人： Micron Technology, Inc.

发明人： Kamal M. Karda ,  Chandra Mouli ,  Durai Vishak Nirmal Ramaswamy ,  F. Daniel Gealy

IPC分类号： G11C11/22 ,  H01L29/788 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H10B51/30

CPC分类号： G11C11/223 ,  H01L29/788 ,  H01L29/42392 ,  H01L29/42324 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/78391 ,  H01L29/4234 ,  H01L29/6684 ,  H10B51/30 ,  H01L29/66825 ,  H01L29/7887 ,  H01L29/7889

摘要： A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. A gate is proximate a periphery of the channel core. A gate insulator is between the gate and the channel core. The gate insulator has local regions radially there-through that have different capacitance at different circumferential locations relative to the channel core periphery. Additional constructions, and methods, are disclosed.

公开(公告)号：US11830945B2

公开(公告)日：2023-11-28

申请号：US17699898

申请日：2022-03-21

申请人： Kabushiki Kaisha Toshiba ,  Toshiba Electronic Devices & Storage Corporation

发明人： Kentaro Ichinoseki ,  Tatsuya Nishiwaki ,  Shingo Sato

IPC分类号： H01L29/78 ,  H01L21/225 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40

CPC分类号： H01L29/7827 ,  H01L21/2253 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/7813

摘要： According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a second electrode, a gate electrode, second semiconductor regions of a second conductivity type, third semiconductor regions of the first conductivity type, and a third electrode. The second electrode is provided in a plurality in second and third directions. Each second electrode opposes a portion of the first semiconductor region in the second and third directions with an insulating layer interposed. The gate electrode is provided around each second electrode. The first semiconductor region includes first regions provided respectively around the second electrodes and the second region provided around the first regions in the second and third directions. Impurity concentration of the first conductivity type in each of the first regions is higher than impurity concentration of the first conductivity type in the second region.