公开(公告)号：US08704690B2

公开(公告)日：2014-04-22

申请号：US13285725

申请日：2011-10-31

Applicant: Arne Aas ,  Gunnar Gangstoe ,  Torgeir Fenheim

Inventor： Arne Aas ,  Gunnar Gangstoe ,  Torgeir Fenheim

IPC: H03M1/06

CPC classification number: G01R19/0092 ,  G01R19/2509 ,  H03M1/0607 ,  H03M1/0656 ,  H03M3/34 ,  H03M3/356

Abstract: A method and system utilized with an analog to digital converter is disclosed. The method and system comprise providing a first conversion on an input signal. In the first conversion, an offset error is added to the input signal to provide a first result. The method and system further includes providing a second conversion on the input signal. In the second conversion, an offset error is subtracted from the input signal to provide a second result. The first and second results are then combined to substantially remove the offset error. A system and method in accordance with the present invention compensates for the accumulated offset error over many samples, thereby achieving much higher accuracy in the offset error compensation.

Abstract translation: 公开了一种使用模数转换器的方法和系统。 该方法和系统包括在输入信号上提供第一转换。 在第一次转换中，偏移误差被添加到输入信号以提供第一结果。 该方法和系统还包括对输入信号提供第二转换。 在第二转换中，从输入信号中减去偏移误差以提供第二结果。 然后组合第一和第二结果以基本上去除偏移误差。 根据本发明的系统和方法补偿多个样本上的累积偏移误差，从而在偏移误差补偿中获得高得多的精度。

公开(公告)号：US20090164170A1

公开(公告)日：2009-06-25

申请号：US12317221

申请日：2008-12-18

Applicant: Kim Brondum LARSEN ,  Mogens Lonberg LAU ,  Flemming Buus BENDIXEN

Inventor： Kim Brondum LARSEN ,  Mogens Lonberg LAU ,  Flemming Buus BENDIXEN

IPC: G06F15/00

CPC classification number: H02P9/007 ,  G01D5/24461 ,  G01D5/24476 ,  H02P2101/15 ,  H03M1/0656 ,  H03M1/24 ,  H03M1/645

Abstract: An electric power generator system is provided with improved power efficiency due to a reduced sensitivity to errors in the sensing of angular rotor position. The system includes a power generator with a rotor, and a position encoder connected to sense angular position of the rotor and to generate a position signal accordingly. A processor receives the position signal, calculates an angular position in response, calculates an estimated angular position based on earlier received position signals, and finally generates a processed angular position based on the calculated angular position and the estimated angular position. This processed angular position is a more reliable measure of the rotor position, reducing the influence of short-term errors in the position signal, allowing normal wind turbine operation during temporary position encoder failure, and allowing an orderly shutdown during complete position encoder failure.

Abstract translation: 发电机系统由于对角度转子位置的检测中的误差的敏感性降低而具有改善的功率效率。 该系统包括具有转子的发电机和连接到感测转子的角位置并相应地产生位置信号的位置编码器。 处理器接收位置信号，计算响应中的角度位置，基于先前接收到的位置信号计算估计的角度位置，并且基于计算的角位置和估计的角位置最终生成经处理的角位置。 该处理的角位置是对转子位置的更可靠的测量，减少位置信号中的短期误差的影响，允许临时位置编码器故障期间的正常风力涡轮机运行，并允许在完成位置编码器故障期间有序关闭。

公开(公告)号：US20170356937A1

公开(公告)日：2017-12-14

申请号：US15180814

申请日：2016-06-13

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Lukas Vaculik ,  Jan Tomecek

IPC: G01R21/133 ,  G01R19/25 ,  G01R13/34 ,  H03M1/50 ,  H03M1/12 ,  G01R13/02

CPC classification number: G01R19/2506 ,  G01R13/0272 ,  G01R13/34 ,  G01R13/345 ,  G01R19/0053 ,  G01R23/02 ,  H03M1/0656 ,  H03M1/12 ,  H03M1/1255

Abstract: A method, apparatus, and energy metering system obtains mains samples of a mains power line signal, performs non-white noise (NWN) filtering of the mains power line signal, obtains adjustable clock source samples of an adjustable clock signal of an adjustable clock oscillator, determines a difference based on the mains samples and the adjustable clock source samples, adjusts an adjustable clock source frequency of the adjustable clock oscillator based on the difference, and applies the adjustable clock source frequency to an analog to digital converter (ADC) to determine a conversion rate of the ADC.

公开(公告)号：US09774345B1

公开(公告)日：2017-09-26

申请号：US15448547

申请日：2017-03-02

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kentaro Yoshioka ,  Masanori Furuta ,  Hiroshi Kubota

IPC: H03M7/04 ,  H03M1/46 ,  H03M1/80

CPC classification number: H03M1/466 ,  H03M1/0656 ,  H03M1/468 ,  H03M1/804

Abstract: A successive approximation register analog-to-digital converter includes a capacitance digital-to-analog converter (CDAC) having, a voltage storing circuit connected to an output terminal of the CDAC and including a plurality of capacitors connected in parallel, an output voltage of the CDAC being stored in a selected one of the capacitors, a selector configured to output a voltage stored in the selected one of the capacitors, a comparator configured to compare a voltage input to an input terminal thereof, which is connected to an output terminal of the CDAC, with a reference voltage, and a successive approximation register configured to control the CDAC based on an output of the comparator, and cyclically control the voltage storing circuit and the selector, such that the output of the selector is output to the output terminal one or more cycles after the output voltage was stored in the selected one of the capacitors.

公开(公告)号：US09438268B2

公开(公告)日：2016-09-06

申请号：US14991368

申请日：2016-01-08

Applicant: SOCIONEXT INC.

Inventor： Yosuke Mitani ,  Takashi Morie ,  Kazuo Matsukawa ,  Masashi Uchida

IPC: H03M3/00 ,  H03M1/06 ,  H03M1/08 ,  H03M1/74

CPC classification number: H03M3/502 ,  H03M1/0656 ,  H03M1/0863 ,  H03M1/742 ,  H03M1/745 ,  H03M3/464

Abstract: This D/A converter includes a plurality of D/A converter elements, each comprising current sources configured to supply output currents to output nodes, and first switches configured to control the output currents. The output nodes are connected to a capacitor section having second switches and a capacitive load. The D/A converter further includes a switch control circuit configured to control the first switches responsive to digital signals, and also control the second switches in accordance with the control of the ON/OFF state of the first switches.

Abstract translation: 该D / A转换器包括多个D / A转换器元件，每个D / A转换器元件包括被配置为向输出节点提供输出电流的电流源和被配置为控制输出电流的第一开关。 输出节点连接到具有第二开关和容性负载的电容器部分。 D / A转换器还包括开关控制电路，其被配置为响应于数字信号来控制第一开关，并且还根据第一开关的接通/断开状态的控制来控制第二开关。

公开(公告)号：US20150146829A1

公开(公告)日：2015-05-28

申请号：US14401597

申请日：2013-03-25

Applicant: Robert Bosch GmbH

Inventor： Thomas Wuchert ,  Matthias Kalisch

IPC: H04B15/00 ,  H04L7/02 ,  H04L27/10

CPC classification number: H04B15/00 ,  G01D3/032 ,  H03M1/0656 ,  H03M1/1245 ,  H04L7/02 ,  H04L27/10

Abstract: A method is provided for suppressing interferences in a sampling process. The method includes the method step of sampling an analog useful signal at a sampling frequency f as well as determining whether an interference amplitude is present. In the presence of an interference amplitude, a stochastic shift of the chronologically equidistant sampling points in time, which are determined by the sampling frequency f, is carried out within a range [=Δt; +Δt] (21) around the equidistant sampling points in time, Δt being the maximum shift. Subsequently, a resampling of the analog useful signal is carried out. It is redetermined whether an interference amplitude is present. In the case of the continuous presence of an interference amplitude, a change in the absolute value of the maximum shift |Δt| is carried out and the process is restarted with the method step of stochastically shifting the sampling points in time.

Abstract translation: 提供了一种用于抑制采样过程中的干扰的方法。 该方法包括以采样频率f对模拟有用信号进行采样以及确定是否存在干扰幅度的方法步骤。 在存在干涉幅度的情况下，由采样频率f确定的时间上等距离采样点的随机偏移在[=＆Dgr; t; +＆Dgr; t]（21）在时间上的等距采样点周围，Dgr; t是最大偏移。 随后，进行模拟有用信号的再采样。 重新确定是否存在干扰幅度。 在连续存在干涉幅度的情况下，最大偏移|＆Dgr; t |的绝对值的变化 并且通过随时随地移动采样点的方法步骤重新开始处理。

公开(公告)号：US08928518B1

公开(公告)日：2015-01-06

申请号：US14014854

申请日：2013-08-30

Applicant: Agilent Technologies, Inc.

Inventor： Dusan Stepanovic

IPC: H03M1/12 ,  H03M1/46

CPC classification number: H03M1/466 ,  H03M1/0656 ,  H03M1/0863

Abstract: A charge redistribution SAR analog-to-digital converter includes a source of a reference voltage, a digital-to-analog converter, and a reset circuit. The digital-to-analog converter includes converter stages that range in significance from most significant to least significant. Each converter stage includes respective capacitors and switches. The switches are controllable to selectively connect the capacitors to the reference voltage or to ground. The capacitors of the converter stages are weighted in capacitance in accordance with significance of the converter stage. The reset circuit is to control the switches to reset the converter stages with a temporal offset between at least two of the converter stages. The temporal offset between the at least two of the converter stages reduces the dependence of the charge drawn from the reference voltage source during each conversion cycle on the sample of an analog input signal converted to a digital value during the conversion cycle.

Abstract translation: 电荷再分配SAR模数转换器包括参考电压源，数模转换器和复位电路。 数模转换器包括从最高有效值到最低有效值的重要性范围的转换器级。 每个转换器级包括相应的电容器和开关。 开关是可控制的，以选择性地将电容器连接到参考电压或接地。 根据转换器级的意义，转换器级的电容器以电容进行加权。 复位电路用于控制开关以在至少两个转换器级之间的时间偏移来重置转换器级。 至少两个转换器级之间的时间偏移降低了在转换周期期间在每个转换周期期间从参考电压源抽取的电荷对在转换周期中转换为数字值的模拟输入信号的采样的依赖性。

公开(公告)号：US20130027236A1

公开(公告)日：2013-01-31

申请号：US13577845

申请日：2011-01-20

Applicant: Tomoyuki Yamase ,  Hidemi Noguchi

Inventor： Tomoyuki Yamase ,  Hidemi Noguchi

IPC: H03M1/12

CPC classification number: H03M1/0656 ,  H03M1/0678 ,  H03M1/0697 ,  H03M1/365

Abstract: An A/D conversion unit performs an A/D conversion operation twice during a hold period of an analog value. In a first conversion operation, the A/D conversion unit compares the analog value with a first reference voltage and outputs a comparison result as first converted data. In a second conversion operation, the A/D conversion unit compares the analog value with a second reference voltage and outputs a comparison result as second converted data. The second reference voltage is a voltage obtained by adding or subtracting a minimum resolution voltage to or from the first reference voltage. A digital processing unit averages errors of the first and second converted data by digital processing to detect an A/D conversion error, and feeds back a detection result to the A/D conversion unit as a control value to perform voltage control.

Abstract translation: A / D转换单元在模拟值的保持期间进行两次A / D转换操作。 在第一转换操作中，A / D转换单元将模拟值与第一参考电压进行比较，并输出比较结果作为第一转换数据。 在第二转换操作中，A / D转换单元将模拟值与第二参考电压进行比较，并将比较结果作为第二转换数据输出。 第二参考电压是通过对或从第一参考电压加或减最小分辨率电压而获得的电压。 数字处理单元通过数字处理对第一和第二转换数据的误差进行平均以检测A / D转换误差，并将检测结果反馈到A / D转换单元作为控制值，以执行电压控制。

公开(公告)号：US20120046894A1

公开(公告)日：2012-02-23

申请号：US13285725

申请日：2011-10-31

Applicant: Arne Aas ,  Gunnar Gangstoe ,  Torgeir Fenheim

Inventor： Arne Aas ,  Gunnar Gangstoe ,  Torgeir Fenheim

IPC: H03M1/06 ,  G01R31/36

CPC classification number: G01R19/0092 ,  G01R19/2509 ,  H03M1/0607 ,  H03M1/0656 ,  H03M3/34 ,  H03M3/356

Abstract: A method and system utilized with an analog to digital converter is disclosed. The method and system comprise providing a first conversion on an input signal. In the first conversion, an offset error is added to the input signal to provide a first result. The method and system further includes providing a second conversion on the input signal. In the second conversion, an offset error is subtracted from the input signal to provide a second result. The first and second results are then combined to substantially remove the offset error. A system and method in accordance with the present invention compensates for the accumulated offset error over many samples, thereby achieving much higher accuracy in the offset error compensation.

Abstract translation: 公开了一种使用模数转换器的方法和系统。 该方法和系统包括在输入信号上提供第一转换。 在第一次转换中，偏移误差被添加到输入信号以提供第一结果。 该方法和系统还包括对输入信号提供第二转换。 在第二转换中，从输入信号中减去偏移误差以提供第二结果。 然后组合第一和第二结果以基本上去除偏移误差。 根据本发明的系统和方法补偿多个样本上的累积偏移误差，从而在偏移误差补偿中获得高得多的精度。

公开(公告)号：US07280061B2

公开(公告)日：2007-10-09

申请号：US11127738

申请日：2005-05-12

Applicant: Victor Dias

Inventor： Victor Dias

IPC: H03M1/66 ,  H03M3/00

CPC classification number: H03M1/0656 ,  H03M1/66 ,  H03M3/336 ,  H03M3/502

Abstract: Method and device for reducing the signal images at the output of a digital/analog converter. In a method for reducing the signal images at the output of a digital/analog converter, a frequency hopping clock generator provides a digital data signal whose data rate is varied according to a frequency hopping method. The digital data signal is converted into an analog signal by a digital/analog converter, the conversion clock being varied according to the frequency hopping method.

Abstract translation: 用于减少数字/模拟转换器输出端的信号图像的方法和装置。 在减少数字/模拟转换器输出端的信号图像的方法中，跳频时钟发生器提供数据数据信号，数据速率根据跳频方法而变化。 数字数据信号由数/模转换器转换为模拟信号，转换时钟根据跳频方式而变化。