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185 条记录 (耗时 0.029 秒)

    Semiconductor memory device having pulse width control circuit
    12.
    发明授权
    Semiconductor memory device having pulse width control circuit 失效
    具有脉冲宽度控制电路的半导体存储器件

    公开(公告)号：US4802131A

    公开(公告)日：1989-01-31

    申请号：US152997

    申请日：1988-02-08

    申请人： Kazuhiro Toyoda

    发明人： Kazuhiro Toyoda

    IPC分类号： G11C11/414 ,  G11C7/22 ,  G11C8/00 ,  G11C8/18 ,  G11C11/34 ,  G11C11/40 ,  G11C11/413 ,  G11C7/00

    CPC分类号： G11C8/00 ,  G11C7/22 ,  G11C8/18

    摘要： A semiconductor memory device including an address change detection circuit and a pulse width control circuit. The pulse width control circuit inhibits the passage of write enable signals having a short pulse width for a predetermined period from the change of the address. After the predetermined period, the control operation in the pulse width control circuit is overridden. Therefore, the write cycle time can be kept down.

    摘要翻译： 一种包括地址变化检测电路和脉冲宽度控制电路的半导体存储器件。 脉冲宽度控制电路在地址变化之后的一定时间内禁止具有短脉冲宽度的写使能信号。 在预定时间段之后，脉冲宽度控制电路中的控制操作被覆盖。 因此，写周期时间可以保持不变。

    Current sensing differential amplifier
    13.
    发明授权
    Current sensing differential amplifier 失效
    电流感应差动放大器

    公开(公告)号：US4766333A

    公开(公告)日：1988-08-23

    申请号：US23184

    申请日：1987-03-09

    申请人： Kenneth J. Mobley

    发明人： Kenneth J. Mobley

    IPC分类号： G11C11/414 ,  G11C7/06 ,  H03F3/45 ,  H03K5/24

    CPC分类号： H03K5/2481 ,  G11C7/062 ,  H03K5/249 ,  G11C2207/063

    摘要： An amplifier for a semiconductor circuit provides two circuit paths between VCC and ground, each including the source-drain path of a corresponding primary transistor. Two inpedances are coupled to respective inputs. The primary transistors are kept in saturation so that the voltage differential between the inputs is minimized but a large voltage differential is developed at outputs located along the two circuit paths. Also, a clamp circuit has a common node coupling the gate electrodes of the primary transistors together. Secondary transistors are included to mimic voltage changes on either input.

    摘要翻译： 用于半导体电路的放大器提供VCC和地之间的两个电路路径，每个包括相应的初级晶体管的源极 - 漏极路径。 两个阻抗耦合到相应的输入端。 主晶体管保持饱和，使得输入之间的电压差最小化，但是在沿着两个电路路径的输出处产生大的电压差。 此外，钳位电路具有将主晶体管的栅电极连接在一起的公共节点。 包含二级晶体管以模拟任一输入端的电压变化。

    Semiconductor memory device having block pairs
    16.
    发明授权
    Semiconductor memory device having block pairs 失效
    具有块对的半导体存储器件

    公开(公告)号：US4692900A

    公开(公告)日：1987-09-08

    申请号：US715835

    申请日：1985-03-25

    申请人： Kazuo Ooami ,  Yasuhisa Sugo ,  Tohru Takeshima

    发明人： Kazuo Ooami ,  Yasuhisa Sugo ,  Tohru Takeshima

    IPC分类号： G11C11/41 ,  G11C8/12 ,  G11C11/34 ,  G11C11/40 ,  G11C11/414 ,  G11C11/416 ,  G11C29/26 ,  G11C29/36 ,  G11C5/06 ,  G11C29/00

    CPC分类号： G11C29/26 ,  G11C11/416 ,  G11C29/36 ,  G11C8/12

    摘要： A semiconductor memory device provided with at least one block pair. Each block contains therein bit line pairs, word lines, memory cells, and circuitry for writing data by cooperating with the bit line pairs. The wiring pattern of the writing part located in one of the blocks is reversed to that of the writing part located in another block adjacent thereto, whereby the two facing bit lines of different blocks assume opposite logic levels when the same data logic is written into all the memory cells.

    摘要翻译： 具有至少一个块对的半导体存储器件。 每个块包含位线对，字线，存储单元和用于通过与位线对协作来写入数据的电路。 位于其中一个块中的写入部分的布线图案与位于与其相邻的另一块中的写入部分的布线图案相反，从而当将相同的数据逻辑写入所有不同块时，不同块的两个相对的位线呈现相反的逻辑电平 记忆细胞。

    Bipolar random access memory
    17.
    发明授权
    Bipolar random access memory 失效
    双极随机存取存储器

    公开(公告)号：US4625299A

    公开(公告)日：1986-11-25

    申请号：US573610

    申请日：1984-01-25

    申请人： Hideaki Isogai ,  Isao Fukushi

    发明人： Hideaki Isogai ,  Isao Fukushi

    IPC分类号： G11C11/41 ,  G11C11/414 ,  G11C11/416 ,  G11C7/00

    CPC分类号： G11C11/416

    摘要： A semiconductor memory device used as a bipolar random access memory including a plurality of pairs of word lines, a plurality of pairs of bit lines, and a plurality of static memory cells located at the intersections of and connected between the pairs of word and bit lines. A plurality of constant current sources are selectively connected to the bit lines. A reading-writing voltage control circuit controls the potential of each bit line during the reading and writing of data and a writing current control circuit controls the current flowing to each bit line during the writing of data into the memory cell. Further, the writing current control circuit connects the constant current source to the reading-writing voltage control circuit in the writing of data to the memory cell. Accordingly, the bipolar random access memory can operate at a high speed with reduced power consumption and without unnecessary current flowing in the peripheral circuits.

    摘要翻译： 一种用作双极性随机存取存储器的半导体存储器件，包括多对字线，多对位线以及多个静态存储器单元，位于字与位线对之间的交叉点处并连接 。 多个恒流源选择性地连接到位线。 读写电压控制电路在读取和写入数据期间控制每个位线的电位，并且写入电流控制电路在将数据写入存储单元期间控制流向每个位线的电流。 此外，写入电流控制电路在将数据写入存储单元时将恒流源连接到读写电压控制电路。 因此，双极性随机存取存储器可以以较低的功耗高速运行，并且在外围电路中不会有不必要的电流流动。

    Semiconductor memory having word line discharge current controller
    18.
    发明授权
    Semiconductor memory having word line discharge current controller 失效
    具有字线放电电流控制器的半导体存储器

    公开(公告)号：US4618944A

    公开(公告)日：1986-10-21

    申请号：US594276

    申请日：1984-03-28

    申请人： Yoshinori Okajima

    发明人： Yoshinori Okajima

    IPC分类号： G11C11/414 ,  G11C11/415 ,  G11C7/00

    CPC分类号： G11C11/415

    摘要： A semiconductor memory comprising at least memory cells, word lines (W.sub.+, W.sub.-), bit lines (BL, BL) and word line discharge circuits to be co-operated together with a word line discharge current controller. The word line discharge current controller is operative to gradually reduce a word line discharge current absorbed from the word line W.sub.- to the word line discharge circuit together with a gradual attenuation of an inverse current from the bit line to the corresponding memory cell.

    摘要翻译： 半导体存储器至少包括与字线放电电流控制器共同操作的存储单元，字线（W +，W-），位线（BL，＆amp; B和B）和字线放电电路。 字线放电电流控制器用于逐渐减少从字线W-吸收到字线放电电路的字线放电电流以及从位线到相应的存储器单元的逆电流的逐渐衰减。

    Static-type semiconductor memory device
    19.
    发明授权
    Static-type semiconductor memory device 失效
    静态型半导体存储器件

    公开(公告)号：US4604729A

    公开(公告)日：1986-08-05

    申请号：US482301

    申请日：1983-04-05

    申请人： Masayoshi Kimoto

    发明人： Masayoshi Kimoto

    IPC分类号： G11C5/00 ,  G11C11/41 ,  G11C11/414 ,  G11C11/416 ,  G11C11/40

    CPC分类号： G11C5/005 ,  G11C11/414 ,  G11C11/416

    摘要： A static-type semiconductor memory device having a holding-current controlling circuit such that the holding current supplied to an unselected-state memory block or memory chip is greater than the holding current supplied to a selected-state memory block or memory chip. The current supplied to the peripheral circuit for the unselected-state memory block or memory chip is smaller than the current supplied to the peripheral circuit for the selected-state memory block or memory chip, whereby destruction of stored data can be prevented.

    摘要翻译： 一种具有保持电流控制电路的静态型半导体存储器件，使得提供给非选择状态存储器块或存储器芯片的保持电流大于提供给选择状态存储块或存储器芯片的保持电流。 提供给未选择状态存储器块或存储器芯片的外围电路的电流小于为选择状态的存储器块或存储器芯片提供给外围电路的电流，从而可以防止存储的数据的破坏。

    Adaptive word line pull down
    20.
    发明授权
    Adaptive word line pull down 失效
    自适应字线下拉

    公开(公告)号：US4357687A

    公开(公告)日：1982-11-02

    申请号：US215298

    申请日：1980-12-11

    申请人： Roger V. Rufford

    发明人： Roger V. Rufford

    IPC分类号： G11C11/414 ,  G11C11/415 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C11/415

    摘要： An adaptive word line pull-down circuit steers a pull-down current only to the word being pulled down and only for the time when that word is being pulled down. The time that it takes for the bottom word line to fall controls how long the pull-down current is steered to the falling word.

    摘要翻译： 自适应字线下拉电路仅将下拉电流引导到正在被拉下的字，并且仅在该字被拉下的时候才引导。 底部字线下降所需的时间控制下拉电流被控制到下降字的时间。