公开(公告)号：US20140178003A1

公开(公告)日：2014-06-26

申请号：US13723651

申请日：2012-12-21

Applicant: Ian A. Young ,  Johanna M. Swan ,  Robert L. Sankman ,  Marko Radosavljevic

Inventor： Ian A. Young ,  Johanna M. Swan ,  Robert L. Sankman ,  Marko Radosavljevic

IPC: G02B6/34

CPC classification number: F41H3/02 ,  G02B6/0008 ,  G02B6/02171 ,  G02B6/34 ,  G03B21/10

Abstract: Described herein are technologies related to passive or active cloaking devices. More particularly, the passive or active cloaking devices utilize input/output grating couplers and waveguides to create an impression of invisibility on an object that is covered by the passive or active cloaking devices.

Abstract translation: 这里描述的是与被动或主动伪装设备相关的技术。 更具体地，被动或主动遮蔽装置利用输入/输出光栅耦合器和波导来在由被动或主动伪装装置覆盖的对象上产生不可见的印象。

公开(公告)号：US20140176417A1

公开(公告)日：2014-06-26

申请号：US13724741

申请日：2012-12-21

Applicant: Ian A. Young ,  Johanna M. Swan ,  Robert L. Sankman ,  Marko Radosavljevic

Inventor： Ian A. Young ,  Johanna M. Swan ,  Robert L. Sankman ,  Marko Radosavljevic

IPC: G09G5/12

CPC classification number: G09G3/002 ,  G06F1/163 ,  G06F1/1639 ,  G06F3/0425 ,  G06F3/147 ,  G09G2370/16 ,  H04N9/3173 ,  H04N9/3185

Abstract: Described herein are technologies related to a wearable projector to project images, information, multimedia, etc. in a portable display. More particularly, the wearable projector includes a system on chip (SOC) microprocessor that is configured to project the images, information, multimedia, etc. to different types of portable display such as, flexible transparent plastic, glass, paper, and the like.

Abstract translation: 这里描述的是与便携式显示器中投射图像，信息，多媒体等的可穿戴式投影仪有关的技术。 更具体地，可穿戴式投影仪包括被配置为将图像，信息，多媒体等投影到诸如柔性透明塑料，玻璃，纸张等不同类型的便携式显示器的片上系统（SOC）微处理器。

公开(公告)号：US08716751B2

公开(公告)日：2014-05-06

申请号：US13631417

申请日：2012-09-28

Applicant: Niti Goel ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Robert S. Chau ,  Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Seung Hoon Sung

Inventor： Niti Goel ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Robert S. Chau ,  Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Seung Hoon Sung

IPC: H01L21/02

CPC classification number: H01L27/092 ,  H01L21/0245 ,  H01L21/02538 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

Abstract: An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

Abstract translation: 一种装置，包括在具有与第一格子结构不同的第二格子结构的缓冲材料中具有匹配的晶格结构的阱材料的阱上具有第一晶格结构的沟道材料的装置。 一种包括在缓冲材料中形成沟槽的方法; 在沟槽中形成n型阱材料，n型阱材料具有与缓冲材料的晶格结构不同的晶格结构; 并形成n型晶体管。 一种包括计算机的系统，包括处理器，所述处理器包括互补的金属氧化物半导体电路，所述辅助金属氧化物半导体电路包括包括沟道材料的n型晶体管，所述沟道材料在布置在具有不同于 第一晶格结构，n型晶体管耦合到p型晶体管。

公开(公告)号：US20140103294A1

公开(公告)日：2014-04-17

申请号：US14106556

申请日：2013-12-13

Applicant: Marko Radosavljevic ,  Gilbert Dewey ,  Niloy Mukherjee ,  Ravi Pillarisetty

Inventor： Marko Radosavljevic ,  Gilbert Dewey ,  Niloy Mukherjee ,  Ravi Pillarisetty

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/7782 ,  B82Y10/00 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848

Abstract: Embodiments of the present disclosure describe techniques and configurations to impart strain to integrated circuit devices such as horizontal field effect transistors. An integrated circuit device includes a semiconductor substrate, a quantum well channel coupled with the semiconductor substrate, a source structure coupled with the quantum well channel, a drain structure coupled with the quantum well channel and a strain-inducing film disposed on and in direct contact with material of the source structure and the drain structure to reduce resistance of the quantum well channel by imparting a tensile or compressive strain on the quantum well channel, wherein the quantum well channel is disposed between the strain-inducing film and the semiconductor substrate. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了为诸如水平场效应晶体管等集成电路器件施加应变的技术和配置。 集成电路器件包括半导体衬底，与半导体衬底耦合的量子阱沟道，与量子阱沟道耦合的源极结构，与量子阱沟道耦合的漏极结构以及直接接触的应变诱导膜 其中源结构和漏极结构的材料通过在量子阱沟道上施加拉伸或压缩应变来降低量子阱沟道的电阻，其中量子阱沟道设置在应变诱导膜和半导体衬底之间。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20140084343A1

公开(公告)日：2014-03-27

申请号：US13629154

申请日：2012-09-27

Applicant: Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Niloy Mukherjee

Inventor： Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Niloy Mukherjee

IPC: H01L29/78 ,  B82Y99/00

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y99/00 ,  H01L29/0665 ,  H01L29/201 ,  H01L29/205 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696

Abstract: Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.

Abstract translation: 描述具有多电介质栅叠层的具有III-V族材料的区域的非平面半导体器件。 例如，半导体器件包括设置在衬底上的异质结构。 异质结构包括具有沟道区的三维III-V族材料体。 源极和漏极材料区域设置在三维III-V族材料体上方。 在源极和漏极材料区域中布置沟槽，其将源极区域与漏极区域分离，并且暴露沟道区域的至少一部分。 栅极堆叠设置在沟槽中和沟道区域的暴露部分上。 栅极堆叠包括第一和第二电介质层和栅电极。

公开(公告)号：US08592803B2

公开(公告)日：2013-11-26

申请号：US13442098

申请日：2012-04-09

Applicant: Ravi Pillarisetty ,  Been-Yin Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

Inventor： Ravi Pillarisetty ,  Been-Yin Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

IPC: H01L29/06 ,  H01L29/778

CPC classification number: H01L27/092 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7782

Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

公开(公告)号：US20130307513A1

公开(公告)日：2013-11-21

申请号：US13976414

申请日：2011-12-19

Applicant: Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

Inventor： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/775 ,  G05F3/02 ,  H01L29/66

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  G05F3/02 ,  H01L21/02603 ,  H01L21/02636 ,  H01L21/225 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/32133 ,  H01L21/324 ,  H01L29/04 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78696

Abstract: Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions.

Abstract translation: 晶体管适用于高电压和高频工作。 纳米线垂直或水平地布置在基底上。 纳米线的纵向长度被限定为第一半导体材料的沟道区域，与沟道区域的第一端电耦合的源极区域，与沟道区域的第二端电耦合的漏极区域和外部漏极 区域设置在沟道区域和漏极区域之间。 外在漏极区具有比第一半导体更宽的带隙。 包括栅极导体和栅极绝缘体的栅极堆叠器完全同轴地包裹在沟道区域周围，漏极和源极触点类似地同轴地围绕漏极和源极区域包裹。

公开(公告)号：US20130240838A1

公开(公告)日：2013-09-19

申请号：US13872966

申请日：2013-04-29

Applicant: Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Niloy Mukherjee

Inventor： Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Niloy Mukherjee

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/7783 ,  B82Y10/00 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/7785 ,  H01L29/7848 ,  H01L29/802 ,  H01L29/803

Abstract: Embodiments of the present disclosure describe structures and techniques to increase carrier injection velocity for integrated circuit devices. An integrated circuit device includes a semiconductor substrate, a first barrier film coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier film, the quantum well channel comprising a first material having a first bandgap energy, and a source structure coupled to launch mobile charge carriers into the quantum well channel, the source structure comprising a second material having a second bandgap energy, wherein the second bandgap energy is greater than the first bandgap energy. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了用于增加集成电路器件的载流子注入速度的结构和技术。 集成电路器件包括半导体衬底，与半导体衬底耦合的第一阻挡膜，耦合到第一阻挡膜的量子阱沟道，该量子阱沟道包括具有第一带隙能量的第一材料和耦合到 将移动电荷载流子发射到量子阱沟道中，源结构包括具有第二带隙能量的第二材料，其中第二带隙能量大于第一带隙能量。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20130164898A1

公开(公告)日：2013-06-27

申请号：US13773558

申请日：2013-02-21

Applicant: Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Gilbert Dewey ,  Jack T. Kavelieros

Inventor： Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Gilbert Dewey ,  Jack T. Kavelieros

IPC: H01L29/66

CPC classification number: H01L29/66522 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/205 ,  H01L29/66477

Abstract: A surface channel transistor is provided in a semiconductive device. The surface channel transistor is either a PMOS or an NMOS device. Epitaxial layers are disposed above the surface channel transistor to cause an increased bandgap phenomenon nearer the surface of the device. A process of forming the surface channel transistor includes grading the epitaxial layers.

Abstract translation: 表面沟道晶体管设置在半导体器件中。 表面沟道晶体管是PMOS或NMOS器件。 外延层设置在表面沟道晶体管的上方，导致更接近器件表面的带隙现象增加。 形成表面沟道晶体管的工艺包括对外延层进行分级。

公开(公告)号：US08440998B2

公开(公告)日：2013-05-14

申请号：US12643848

申请日：2009-12-21

Applicant: Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Niloy Mukherjee

Inventor： Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Niloy Mukherjee

IPC: H01L29/06

CPC classification number: H01L29/7783 ,  B82Y10/00 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/7785 ,  H01L29/7848 ,  H01L29/802 ,  H01L29/803

Abstract: Embodiments of the present disclosure describe structures and techniques to increase carrier injection velocity for integrated circuit devices. An integrated circuit device includes a semiconductor substrate, a first barrier film coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier film, the quantum well channel comprising a first material having a first bandgap energy, and a source structure coupled to launch mobile charge carriers into the quantum well channel, the source structure comprising a second material having a second bandgap energy, wherein the second bandgap energy is greater than the first bandgap energy. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了用于增加集成电路器件的载流子注入速度的结构和技术。 集成电路器件包括半导体衬底，与半导体衬底耦合的第一阻挡膜，耦合到第一阻挡膜的量子阱沟道，该量子阱沟道包括具有第一带隙能量的第一材料和耦合到 将移动电荷载流子发射到量子阱沟道中，源结构包括具有第二带隙能量的第二材料，其中第二带隙能量大于第一带隙能量。 可以描述和/或要求保护其他实施例。