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    Cavities containing multi-wiring structures and devices
    191.
    发明授权
    Cavities containing multi-wiring structures and devices 有权

    公开(公告)号：US10813214B2

    公开(公告)日：2020-10-20

    申请号：US16007410

    申请日：2018-06-13

    Applicant: Invensas Corporation

    Inventor： Cyprian Emeka Uzoh ,  Craig Mitchell ,  Belgacem Haba ,  Ilyas Mohammed

    IPC: H01K3/10 ,  H05K1/02 ,  H01L23/498 ,  H05K1/11 ,  H05K3/42 ,  H01R12/71

    Abstract: A method for making an interconnection component includes forming a mask layer that covers a first opening in a sheet-like element that includes a first opening extending between the first and second surfaces of the element. The element consists essentially of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. The first opening includes a central opening and a plurality of peripheral openings open to the central opening that extends in an axial direction of the central opening. A conductive seed layer can cover an interior surface of the first opening. The method further includes forming a first mask opening in at least a portion of the mask layer overlying the first opening to expose portions of the conductive seed layer within the peripheral openings; and forming electrical conductors on exposed portions of the conductive seed layer.

    FLAT METAL FEATURES FOR MICROELECTRONICS APPLICATIONS
    194.
    发明申请
    FLAT METAL FEATURES FOR MICROELECTRONICS APPLICATIONS 审中-公开

    公开(公告)号：US20190393086A1

    公开(公告)日：2019-12-26

    申请号：US16563512

    申请日：2019-09-06

    Applicant: Invensas Corporation

    Inventor： Cyprian Emeka Uzoh

    IPC: H01L21/768

    Abstract: Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features.

    Flat metal features for microelectronics applications
    195.
    发明授权
    Flat metal features for microelectronics applications 有权

    公开(公告)号：US10446441B2

    公开(公告)日：2019-10-15

    申请号：US15994435

    申请日：2018-05-31

    Applicant: Invensas Corporation

    Inventor： Cyprian Emeka Uzoh

    IPC: H01L21/768 ,  H01L23/488 ,  H01L23/00 ,  H01L23/532

    Abstract: Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features.

    Hybrid 3D/2.5D interposer
    197.
    发明授权
    Hybrid 3D/2.5D interposer 有权

    公开(公告)号：US10177114B2

    公开(公告)日：2019-01-08

    申请号：US14952482

    申请日：2015-11-25

    Applicant: Invensas Corporation

    Inventor： Charles G. Woychik ,  Cyprian Emeka Uzoh ,  Sangil Lee ,  Liang Wang ,  Guilian Gao

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L23/31

    Abstract: Representative implementations of devices and techniques provide a hybrid interposer for 3D or 2.5D package arrangements. A quantity of pockets is formed on a surface of a carrier in a predetermined pattern. The pockets are filled with a reflowable conductive material. Chip dice are coupled to the interposer carrier by fixing terminals of the dice into the pockets. The carrier may include topside and backside redistribution layers to provide fanout for the chip dice, for coupling the interposer to another carrier, board, etc. having a pitch greater than that of the chip dice.

    Capacitors using porous alumina structures
    198.
    发明授权
    Capacitors using porous alumina structures 有权

    公开(公告)号：US10147548B2

    公开(公告)日：2018-12-04

    申请号：US14733269

    申请日：2015-06-08

    Applicant: Invensas Corporation

    Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh

    IPC: H01G4/33 ,  H01G4/08 ,  H01G4/01 ,  H01G4/10 ,  H01L49/02 ,  H01M4/80 ,  H01G4/38

    Abstract: Capacitors and methods of making the same are disclosed herein. In one embodiment, a capacitor comprises a structure having first and second oppositely facing surfaces and a plurality of pores each extending in a first direction from the first surface towards the second surface, and each having pore having insulating material extending along a wall of the pore; a first conductive portion comprising an electrically conductive material extending within at least some of the pores; and a second conductive portion comprising a region of the structure consisting essentially of aluminum surrounding individual pores of the plurality of pores, the second conductive portion electrically isolated from the first conductive portion by the insulating material extending along the walls of the pores.

    Ultra high performance interposer
    199.
    发明授权
    Ultra high performance interposer 有权

    公开(公告)号：US10032715B2

    公开(公告)日：2018-07-24

    申请号：US15601406

    申请日：2017-05-22

    Applicant: Invensas Corporation

    Inventor： Cyprian Emeka Uzoh ,  Zhuowen Sun

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/522 ,  H01L21/48 ,  H01L21/768 ,  H01L23/14 ,  H01L23/498

    Abstract: An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.

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