公开(公告)号：US09330777B2

公开(公告)日：2016-05-03

申请号：US14632556

申请日：2015-02-26

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Mark Helm ,  Pranav Kalavade ,  Charan Srinivasan

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/30 ,  G11C16/10

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459

Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying, during a first pass of programming, a first bias voltage value to a source select gate to isolate memory cells from a source, applying a programming voltage to an access line of a page of the memory cells during the first pass of programming, and applying a second bias voltage value to the source select gate to isolate the memory cells from the source during a second pass of programming. Further devices, systems, and methods are disclosed.

公开(公告)号：US20160049417A1

公开(公告)日：2016-02-18

申请号：US14925589

申请日：2015-10-28

Applicant: Micron Technology, Inc.

Inventor： Charles H. Dennison ,  Akira Goda ,  John Hopkins ,  Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L27/115 ,  H01L29/66

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L27/11578 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

Abstract translation: 垂直存储器中的浮动存储单元。 控制栅极形成在介电材料的第一层和第二层电介质材料之间。 浮动栅极形成在介电材料的第一层和第二层介质材料之间，其中浮动栅极包括朝向控制栅极延伸的突起。 在浮置栅极和控制栅极之间形成电荷阻挡结构，其中电荷阻挡结构的至少一部分围绕突起卷绕。

公开(公告)号：US20150287472A1

公开(公告)日：2015-10-08

申请号：US14746416

申请日：2015-06-22

Applicant: Micron Technology, Inc.

Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

IPC: G11C16/32 ,  G11C16/04

CPC classification number: G11C16/3459 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2213/71

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

Abstract translation: 一些实施例包括具有存储单元串的装置和方法，所述存储单元串包括位于装置的不同级别中的存储器单元和耦合到存储单元串的数据线。 存储单元串包括与存储单元相关联的柱体。 这种装置中的至少一个可以包括被配置为在存储器单元之间存储信息到存储器单元中的模块和/或确定存储器单元中存储在存储单元中的信息的值。 该模块还可以被配置为向数据线和/或源施加具有正值的电压以控制身体的电位。 描述其他实施例。

公开(公告)号：US20150206592A1

公开(公告)日：2015-07-23

申请号：US14159198

申请日：2014-01-20

Applicant: Micron Technology, Inc.

Inventor： Akira Goda

IPC: G11C16/34

CPC classification number: G11C16/3427 ,  G11C5/146 ,  G11C7/222 ,  G11C16/10 ,  H01L27/11546

Abstract: Memory devices are disclosed, such as those that include a semiconductor-on-insulator (SOI) NAND memory array having a boosting plate. The boosting plate may be disposed in an insulator layer of the SOI substrate such that the boosting plate exerts a capacitive coupling effect on a p-well of the memory array. Such a boosting plate may be used to boost the p-well during program and erase operations of the memory array. During a read operation, the boosting plate may be grounded to minimize interaction with p-well. Systems including the memory array and methods of operating the memory array are also disclosed.

Abstract translation: 公开了存储器件，例如包括具有升压板的绝缘体上半导体（SOI）NAND存储器阵列的存储器件。 升压板可以设置在SOI衬底的绝缘体层中，使得升压板对存储器阵列的p阱施加电容耦合效应。 这种升压板可用于在存储器阵列的编程和擦除操作期间升压p阱。 在读取操作期间，升压板可以接地以最小化与p阱的相互作用。 还公开了包括存储器阵列的系统和操作存储器阵列的方法。

公开(公告)号：US20140198579A1

公开(公告)日：2014-07-17

申请号：US14164307

申请日：2014-01-27

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Akira Goda

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3454

Abstract: Apparatuses and methods for disturb verify for programming operations are described. Programming memory cells can include applying a number of programming pulses to a first memory cell, performing a disturb verify operation on a second memory cell adjacent to the first memory cell, and inhibiting the first memory cell from further programming in response to the second memory cell failing the disturb verify operation. Other apparatuses and methods are also disclosed.

Abstract translation: 描述用于编程操作的干扰校验的装置和方法。 编程存储器单元可以包括将多个编程脉冲施加到第一存储器单元，对与第一存储器单元相邻的第二存储单元执行干扰校验操作，以及响应于第二存储器单元禁止第一存储器单元进一步编程 无法进行干扰验证操作。 还公开了其它装置和方法。

公开(公告)号：US20130332769A1

公开(公告)日：2013-12-12

申请号：US13970055

申请日：2013-08-19

Applicant: Micron Technology, Inc.

Inventor： Krishna K. Parat ,  Akira Goda ,  Koichi Kawai ,  Brian J. Soderling ,  Jeremy Binfet ,  Arnaud A. Furnemont ,  Tejas Krishnamohan ,  Tyson M. Stichka ,  Giuseppina Puzzilli

IPC: G11C29/00

CPC classification number: G11C29/765 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/349 ,  G11C29/789

Abstract: Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select gate transistors. The block is retired from use if the number of bad strings exceeds a threshold. Additional embodiments are disclosed.

Abstract translation: 公开了存储器件和方法，包括涉及擦除存储器单元块的方法。 在擦除块之后，并且在块的后续编程之前，基于选择栅晶体管上的电荷积累来确定块中的多个不良串。 如果坏字符串的数量超过阈值，则该块将从使用中退出。 公开了另外的实施例。

公开(公告)号：US20130137229A1

公开(公告)日：2013-05-30

申请号：US13746578

申请日：2013-01-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Akira Goda

IPC: H01L29/66

CPC classification number: H01L29/66666 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

Abstract: Memory arrays and their formation are disclosed. One such memory array has a string of series-coupled memory cells with a substantially vertical portion. A distance between adjacent memory cells at one end of the substantially vertical portion is greater than a distance between adjacent memory cells at an opposing end of the substantially vertical portion. For other embodiments, thicknesses of respective control gates of the memory cells and/or thicknesses of the dielectrics between successively adjacent control gates may increase as the distances of the respective control gates/dielectrics from the opposing end of the substantially vertical portion increase.

Abstract translation: 公开了存储器阵列及其形成。 一个这样的存储器阵列具有串联耦合的存储器单元串，其具有基本垂直的部分。 在基本垂直部分的一端处的相邻存储单元之间的距离大于在基本垂直部分的相对端处的相邻存储单元之间的距离。 对于其他实施例，存储单元的相应控制栅极的厚度和/或连续相邻的控制栅极之间的电介质的厚度可以随着各个控制栅极/电介质与基本垂直部分的相对端的距离增加而增加。

公开(公告)号：US20250130736A1

公开(公告)日：2025-04-24

申请号：US18901899

申请日：2024-09-30

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Akira Goda ,  Huai-Yuan Tseng ,  David Scott Ebsen

IPC: G06F3/06

Abstract: A processing device in a memory sub-system determines that an amount of host data in a first portion of a memory device configured as a program buffer satisfies a buffer threshold criterion and initiates an initial program pass of first host data from the program buffer to a second portion of the memory device configured as a primary memory. The processing device further determines that the first host data is to be evicted from the program buffer, and initiating a final program pass of the first host data from the program buffer to the primary memory.

公开(公告)号：US20250087275A1

公开(公告)日：2025-03-13

申请号：US18768970

申请日：2024-07-10

Applicant: Micron Technology, Inc.

Inventor： Shyam Sunder Raghunathan ,  Yingda Dong ,  Akira Goda

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/28

Abstract: An apparatus can comprise a memory array comprising a plurality of strings of memory cells. A first string of the plurality of strings can comprises: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is coupled to the memory array and configured to, in order to selectively erase the second erase block independently of the first erase block: apply a voltage having a first value to a sense line coupled to the plurality of strings; apply a voltage having a second value less than the first value to the first group of access lines; and apply a voltage having a third value less than the second value to the second group of access lines.

公开(公告)号：US12217799B2

公开(公告)日：2025-02-04

申请号：US18119997

申请日：2023-03-10

Applicant: Micron Technology, Inc.

Inventor： Paing Z. Htet ,  Akira Goda ,  Eric N. Lee ,  Jeffrey S. McNeil ,  Junwyn A. Lacsao ,  Kishore Kumar Muchherla ,  Sead Zildzic ,  Violante Moschiano

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.