公开(公告)号：US07005700B2

公开(公告)日：2006-02-28

申请号：US10751860

申请日：2004-01-06

Applicant: Jong Ho Lee

Inventor： Jong Ho Lee

IPC: H01L29/788

CPC classification number: B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/7881

Abstract: The conventional flash memory device is fabricated by the MOS processing technology on a bulk substrate and has a similar configuration to an MOS device.While the conventional CMOS device has a superior scaling down characteristic, the scaling down characteristic of a flash memory device is poor due to the inability to reduce the thickness below 7 nm or 8 nm for the tunneling oxide film where the charges in the channel are tunneled into the floating electrode through the tunneling oxide.In order to resolve this problem, the present invention, instead of a SOI wafer, uses a cheaper bulk silicon wafer with lower defect density. A wall shape Fin active region where the channel and the source/drain are formed is connected to the bulk silicon substrate by which floating body effect and heat conduction problem are resolved. a flash memory device is fabricated by forming a tunneling oxide film on side surfaces of the Fin active and a floating (storage) electrode where the charges could be stored.The above structure has a superior scaling down characteristic and enhanced memory performance due to a double-gate flash memory device structure.

Abstract translation: 传统的闪速存储器件通过MOS处理技术在大容量衬底上制造并且具有与MOS器件相似的配置。

公开(公告)号：US20060022252A1

公开(公告)日：2006-02-02

申请号：US11193231

申请日：2005-07-29

Applicant: Seok-Joo Doh ,  Jong-Pyo Kim ,  Jong-Ho Lee ,  Ki-Chul Kim

Inventor： Seok-Joo Doh ,  Jong-Pyo Kim ,  Jong-Ho Lee ,  Ki-Chul Kim

IPC: H01L29/76

CPC classification number: H01L29/513 ,  H01L29/792

Abstract: There are provided a nonvolatile memory device and a method of fabricating the same. A gate region of the nonvolatile memory device is formed as a stack structure including a tunnel oxide layer, a trapping layer, a blocking layer and a control gate electrode. The trapping layer is formed of a high-k dielectric having a higher dielectric constant than that of the tunnel oxide layer. When the trapping layer is formed of high-k dielectric, an EOT in a same thickness can be reduced, and excitation of electrons of the control gate electrode to the tunnel oxide layer due to a high potential barrier relative to the tunnel oxide layer is prevented so that program and erase voltages can be further reduced. As such, a problem that the tunnel oxide layer is damaged due to the conventional high program and erase voltages can be solved by reducing the program and erase voltages, and program and erase speeds of the transistor can be further improved.

Abstract translation: 提供了一种非易失性存储器件及其制造方法。 非易失性存储器件的栅极区域形成为包括隧道氧化物层，俘获层，阻挡层和控制栅电极的堆叠结构。 捕获层由具有比隧道氧化物层的介电常数更高的介电常数的高k电介质形成。 当捕获层由高k电介质形成时，可以减小相同厚度的EOT，并且防止由于相对于隧道氧化物层的高势垒而使控制栅电极的电子激发到隧道氧化物层 从而可以进一步减少编程和擦除电压。 因此，通过减少编程和擦除电压可以解决隧道氧化物层由于常规的高编程和擦除电压而损坏的问题，并且可以进一步提高晶体管的编程和擦除速度。

公开(公告)号：US20060003507A1

公开(公告)日：2006-01-05

申请号：US11044968

申请日：2005-01-27

Applicant: Hyung-Suk Jung ,  Jong-Ho Lee ,  Hwa-Sung Rhee ,  Jae-Kwang Choi

Inventor： Hyung-Suk Jung ,  Jong-Ho Lee ,  Hwa-Sung Rhee ,  Jae-Kwang Choi

IPC: H01L21/336

CPC classification number: H01L21/823857 ,  H01L21/28194 ,  H01L21/3141 ,  H01L21/31608 ,  H01L21/31645 ,  H01L21/823842 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuit devices include a semiconductor substrate having a first doped region and a second doped region having a different doping type than the first doped region. A gate electrode structure on the semiconductor substrate extends between the first and second doped regions and has a gate insulation layer of a first high dielectric constant material in the first doped region and of a second high dielectric constant material, different from the first high dielectric constant material, in the second doped region. A gate electrode is on the gate insulation layer.

Abstract translation: 集成电路器件包括具有第一掺杂区域和具有与第一掺杂区域不同的掺杂类型的第二掺杂区域的半导体衬底。 半导体衬底上的栅极电极结构在第一和第二掺杂区域之间延伸，并且在第一掺杂区域中具有第一高介电常数材料的栅极绝缘层和不同于第一高介电常数的第二高介电常数材料 材料，在第二掺杂区域。 栅极电极位于栅极绝缘层上。

公开(公告)号：US20050206494A1

公开(公告)日：2005-09-22

申请号：US10888309

申请日：2004-07-09

Applicant: Chang-Mo Ko ,  Su-An Choi ,  Jun-Ku Han ,  An-Na Lee ,  Jong-Hwan Lee ,  Ju-Dam Kim ,  Jong-Ho Lee ,  Jong-Seo Yoon

Inventor： Chang-Mo Ko ,  Su-An Choi ,  Jun-Ku Han ,  An-Na Lee ,  Jong-Hwan Lee ,  Ju-Dam Kim ,  Jong-Ho Lee ,  Jong-Seo Yoon

IPC: H01C7/02 ,  H01C1/144 ,  H01C7/00 ,  H01C7/10 ,  H01C7/13 ,  H01M2/10 ,  H01M2/34 ,  H01M10/48

CPC classification number: H01C7/008 ,  H01C1/144

Abstract: A thermistor of which resistance is changed depending on temperature and a secondary battery to which the thermistor is attached are disclosed. The thermistor is attached to an object via a lead which is made of different kinds of materials. The lead is configured so that a part of the lead to be united to the thermistor electrode is mainly made of the same material as the electrode and a part of the lead to be united to the object is mainly made of the same material as the surface of the object. Thus, the thermistor may be simply attached to the object only using the ultrasonic welding, thereby remarkably reducing junction inferiorities.

Abstract translation: 公开了根据温度改变电阻的热敏电阻和附接有热敏电阻的二次电池。 热敏电阻通过由不同种类的材料制成的引线附着到物体上。 引线被配置为使得与热敏电阻电极相结合的引线的一部分主要由与电极相同的材料制成，并且与物体结合的引线的一部分主要由与表面相同的材料制成 的对象。 因此，热敏电阻可以仅使用超声波焊接简单地附接到物体，从而显着地减少了接合性。

公开(公告)号：US20050107876A1

公开(公告)日：2005-05-19

申请号：US11019441

申请日：2004-12-21

Applicant: Ki-Ho Kim ,  Eun-Kyung Yang ,  Sung-Po Kim ,  Kang-Il Ko ,  Jong-Won Lee ,  Hyun-Mi Chang ,  Jong-Ho Lee ,  Ki-Hwan Han ,  Dae-Gu Son

Inventor： Ki-Ho Kim ,  Eun-Kyung Yang ,  Sung-Po Kim ,  Kang-Il Ko ,  Jong-Won Lee ,  Hyun-Mi Chang ,  Jong-Ho Lee ,  Ki-Hwan Han ,  Dae-Gu Son

IPC: A61F2/10 ,  A61L27/24 ,  A61L27/56 ,  A61L27/58 ,  A61L27/60

CPC classification number: A61L27/58 ,  A61L27/24 ,  A61L27/3604 ,  A61L27/56 ,  A61L27/60

Abstract: The present invention relates to a dermal substitute comprising the biodegradable polymer such as collagen and the biomaterial such as amnion, the preparation method and the use thereof. Specifically, the present invention provides with an amnion-collagen sponge complex structure prepared by attaching, inserting or incorporating an amnion obtained from placenta to/in collagen. Inventive dermal substitute can be applied to surgery and wound requiring skin graft, for example, severe burns such as second-degree burn, without rejection by immune system. Further, inventive dermal substitute with amnion instead of silicone membrane has several advantages, such as better biocompatibility, anti-inflammatory activity and promoting activity of wound healing and commercial utilization as basement membrane. Also, inventive complex structure can be used as the basic matrix of bio-artificial skin for culturing cells and the biodegradable basic matrix for preparing artificial organs.

Abstract translation: 本发明涉及包含生物可降解聚合物如胶原和生物材料如羊膜的真皮替代品，其制备方法和用途。 具体地，本发明提供了通过将从胎盘获得的羊膜附着，插入或并入到胶原中的方式制备的羊膜胶原海绵复合结构。 本发明的皮肤替代物可应用于需要皮肤移植的手术和伤口，例如严重烧伤，例如二次烧伤，无免疫系统排斥。 此外，本发明的用羊膜代替硅酮膜的皮肤替代物具有几个优点，例如更好的生物相容性，抗炎活性和促进伤口愈合的活性和作为基底膜的商业利用。 此外，本发明的复合结构可用作培养细胞的生物人造皮肤的基质和用于制备人造器官的可生物降解的碱性基质。

公开(公告)号：US20050046273A1

公开(公告)日：2005-03-03

申请号：US10911708

申请日：2004-08-04

Applicant: In-Yong Jung ,  Jae-Hwan Jeon ,  Jong-Ho Lee

Inventor： In-Yong Jung ,  Jae-Hwan Jeon ,  Jong-Ho Lee

IPC: B60T8/17 ,  B60T7/02 ,  B60T7/04 ,  B60T7/06 ,  F16F9/53 ,  B60T13/74

CPC classification number: B60T7/042 ,  G05G1/44 ,  G05G5/03 ,  Y10T74/20528 ,  Y10T74/20888

Abstract: A torsion spring is equipped to provide a resilient force toward an opposite direction of a manipulation force of a driver's pedal and an MR damper is equipped to promptly actively attenuate the resilient force of the torsion spring and the manipulation force of the driver's pedal. Thereby, contributing to a wide control range of the reaction force of the pedal, an effective response, and a proper formation of hysteresis of the reaction force of the pedal.

Abstract translation: 扭转弹簧装备成朝着与驾驶员踏板的操纵力相反的方向提供弹力，并且MR阻尼器被配备成能够迅速地主动地衰减扭簧的弹力和驾驶员踏板的操纵力。 因此，有助于踏板的反作用力的大的控制范围，有效的响应以及踏板的反作用力的适当的迟滞形成。

公开(公告)号：US20050037630A1

公开(公告)日：2005-02-17

申请号：US10659945

申请日：2003-09-10

Applicant: Seok-Joo Doh ,  Hyung-suk Jung ,  Nae-in Lee ,  Jong-ho Lee ,  Yun-seok Kim

Inventor： Seok-Joo Doh ,  Hyung-suk Jung ,  Nae-in Lee ,  Jong-ho Lee ,  Yun-seok Kim

IPC: H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L29/51 ,  H01L21/31 ,  H01L21/469

CPC classification number: H01L21/02329 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3143 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31662 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates or ozone oxide layers over silicon substrates may be nitrided and post thermally treated by oxidation, annealing, or a combination of oxidation and annealing to form high dielectric layers having superior mobility and interfacial characteristics.

Abstract translation: 可以将通过氧化，退火，氧化，氧化，氧化，氧化，氧化钇和/或其他金属氧化物和/或硅衬底上的其它金属氧化物和硅酸盐形成的高介电层氮化和后热处理， 或氧化和退火的组合以形成具有优异迁移率和界面特性的高介电层。

公开(公告)号：US06768158B2

公开(公告)日：2004-07-27

申请号：US10234501

申请日：2002-09-04

Applicant: Jong Ho Lee ,  Hyung Cheol Shin

Inventor： Jong Ho Lee ,  Hyung Cheol Shin

IPC: H01L29788

CPC classification number: H01L21/28273 ,  H01L29/42324 ,  H01L29/785 ,  H01L29/7854 ,  H01L29/7881 ,  H01L29/792

Abstract: The present invention provides a flash memory element and its manufacturing method having improved overall memory characteristics by constituting a double-gate element for improving the scaling down characteristic of flash memory element. With the above double-gate flash memory structure, a flash memory element in the present invention improves the scaling down characteristic and the programming and retention characteristic of a flash memory element.

Abstract translation: 本发明提供了一种闪速存储元件及其制造方法，通过构成用于提高闪存元件的缩小特性的双栅极元件，具有改进的总体存储器特性。 利用上述双栅闪存结构，本发明中的闪速存储元件提高了闪存元件的缩小特性和编程和保持特性。

公开(公告)号：US06509210B2

公开(公告)日：2003-01-21

申请号：US09736205

申请日：2000-12-15

Applicant: Young June Park ,  Jong Ho Lee ,  Hyeok Jae Lee

Inventor： Young June Park ,  Jong Ho Lee ,  Hyeok Jae Lee

IPC: H01L2100

CPC classification number: H01L29/66757 ,  H01L21/764

Abstract: A semiconductor device and method of fabricating the same. The semiconductor device includes a first insulating film formed on a substrate and having a plurality of holes therein; a cavity formed under the first insulating film; an impurity region formed in the substrate and around the cavity; a second insulating film formed on portions of the first insulating film to fill the holes and a space between the cavity and the impurity region; a plurality of contact holes formed to expose certain portions of the impurity region; and a plurality of wiring layers formed to be in contact with the impurity region through the contact holes.

Abstract translation: 一种半导体器件及其制造方法。 半导体器件包括形成在衬底上并在其中具有多个孔的第一绝缘膜; 形成在所述第一绝缘膜下面的空腔; 形成在所述基板中并且围绕所述空腔的杂质区域; 形成在第一绝缘膜的部分上以填充孔的第二绝缘膜和空腔与杂质区之间的空间; 形成为暴露所述杂质区域的某些部分的多个接触孔; 以及形成为通过接触孔与杂质区域接触的多个布线层。

公开(公告)号：US06191467B1

公开(公告)日：2001-02-20

申请号：US09307033

申请日：1999-05-07

Applicant: Young June Park ,  Jong Ho Lee ,  Hyeok Jae Lee

Inventor： Young June Park ,  Jong Ho Lee ,  Hyeok Jae Lee

IPC: H01L2978

CPC classification number: H01L29/66757 ,  H01L21/764

Abstract: A semiconductor device and method of fabricating the same. The semiconductor device includes a first insulating film formed on a substrate and having a plurality of holes therein; a cavity formed under the first insulating film; an impurity region formed in the substrate and around the cavity; a second insulating film formed on portions of the first insulating film to fill the holes and a space between the cavity and the impurity region; a plurality of contact holes formed to expose certain portions of the impurity region; and a plurality of wiring layers formed to be in contact with the impurity region through the contact holes.

Abstract translation: 一种半导体器件及其制造方法。 半导体器件包括形成在衬底上并在其中具有多个孔的第一绝缘膜; 形成在所述第一绝缘膜下面的空腔; 形成在所述基板中并且围绕所述空腔的杂质区域; 形成在第一绝缘膜的部分上以填充孔的第二绝缘膜和空腔和杂质区之间的空间; 形成为暴露所述杂质区域的某些部分的多个接触孔; 以及形成为通过接触孔与杂质区域接触的多个布线层。