公开(公告)号：US20230369443A1

公开(公告)日：2023-11-16

申请号：US18358668

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Ning Yao ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Wei-Yang Lee ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L21/3213

CPC classification number: H01L29/4991 ,  H01L29/66795 ,  H01L29/42364 ,  H01L29/41791 ,  H01L21/32135

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin formed on a substrate; and a gate structure disposed over a channel region of the semiconductor fin, the gate structure including a gate dielectric layer and a gate electrode, wherein the gate dielectric layer includes a bottom portion and a side portion, and the gate electrode is separated from the side portion of the gate dielectric layer by a first air gap.

公开(公告)号：US20230307515A1

公开(公告)日：2023-09-28

申请号：US18328520

申请日：2023-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei Hsu ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L29/786 ,  H01L29/423 ,  H01L21/8234

CPC classification number: H01L29/41733 ,  H01L29/78696 ,  H01L29/42392 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823412

Abstract: A semiconductor device includes a first interconnect structure and multiple channel layers stacked over the first interconnect structure. A bottommost one of the multiple channel layers is thinner than rest of the multiple channel layers. The semiconductor device further includes a gate stack wrapping around each of the channel layers except a bottommost one of the channel layers; a source/drain feature adjoining the channel layers; a first conductive via connecting the first interconnect structure to a bottom of the source/drain feature; and a dielectric feature under the bottommost one of the channel layers and directly contacting the first conductive via.

公开(公告)号：US20230298943A1

公开(公告)日：2023-09-21

申请号：US18323907

申请日：2023-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Huan-Chieh Su ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L23/528 ,  H01L21/764 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/417

CPC classification number: H01L21/823475 ,  H01L27/0886 ,  H01L23/528 ,  H01L21/823431 ,  H01L21/764 ,  H01L21/31053 ,  H01L21/02274 ,  H01L29/41791

Abstract: A semiconductor structure has a frontside and a backside. The semiconductor structure includes an isolation structure at the backside; one or more transistors at the frontside, wherein the one or more transistors have source/drain epitaxial features; two metal plugs through the isolation structure and contacting two of the source/drain electrodes from the backside; and a dielectric liner filling a space between the two metal plugs, wherein the dielectric liner partially or fully surrounds an air gap between the two metal plugs.

公开(公告)号：US11742415B2

公开(公告)日：2023-08-29

申请号：US17178006

申请日：2021-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Shi Ning Ju ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/762 ,  H01L27/088 ,  H01L29/78 ,  H01L21/308

CPC classification number: H01L29/6681 ,  H01L21/3086 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/785

Abstract: FinFET patterning methods are disclosed for achieving fin width uniformity. An exemplary method includes forming a mandrel layer over a substrate. A first cut removes a portion of the mandrel layer, leaving a mandrel feature disposed directly adjacent to a dummy mandrel feature. The substrate is etched using the mandrel feature and the dummy mandrel feature as an etch mask, forming a dummy fin feature and an active fin feature separated by a first spacing along a first direction. A second cut removes a portion of the dummy fin feature and a portion of the active fin feature, forming dummy fins separated by a second spacing and active fins separated by the second spacing. The second spacing is along a second direction substantially perpendicular to the first direction. A third cut removes the dummy fins, forming fin openings, which are filled with a dielectric material to form dielectric fins.

公开(公告)号：US11735594B2

公开(公告)日：2023-08-22

申请号：US17341142

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzer-Min Shen ,  Zhiqiang Wu ,  Chung-Cheng Wu ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Min Cao

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/786 ,  H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/04

CPC classification number: H01L27/1207 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/7869 ,  H01L21/823878 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/7853

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a crystalline direction along the first direction.

公开(公告)号：US20230215948A1

公开(公告)日：2023-07-06

申请号：US18182910

申请日：2023-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L29/49 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/41791 ,  H01L29/4991 ,  H01L29/7851 ,  H01L29/401 ,  H01L29/66795

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a spacer extending along a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact, a gate contact via over and electrically coupled to the gate structure, and a source/drain contact via over and electrically coupled to the source/drain contact. The gate contact via extends through a first dielectric layer such that a portion of the first dielectric layer interposes between the gate contact via and the spacer. The source/drain contact via extends through a second dielectric layer such that a portion of the second dielectric layer interposes between the source/drain contact via and the liner.

公开(公告)号：US11695076B2

公开(公告)日：2023-07-04

申请号：US17193732

申请日：2021-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wang ,  Chih-Chao Chou ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Jui-Chien Huang ,  Chun-Hsiung Lin ,  Chih-Hao Wang

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285

CPC classification number: H01L29/78618 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28518 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78684 ,  H01L29/78696

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.

公开(公告)号：US11688736B2

公开(公告)日：2023-06-27

申请号：US17657941

申请日：2022-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Yang Chuang ,  Jia-Chuan You ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823431 ,  H01L29/0665 ,  H01L29/6681 ,  H01L29/7851 ,  H01L29/7855

Abstract: A method of fabricating a semiconductor device includes providing a dummy structure having a plurality of channel layers, an inner spacer disposed between adjacent channels of the plurality of channel layers and at a lateral end of the channel layers, and a gate structure including a gate dielectric layer and a metal layer interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. A metal gate etching process is performed to remove the metal layer from the gate structure while the gate dielectric layer remains disposed at a channel layer-inner spacer interface. After performing the metal gate etching process, a dry etching process is performed to form a cut region along the active edge. The gate dielectric layer disposed at the channel layer-inner spacer interface prevents the dry etching process from damaging a source/drain feature within the adjacent active region.

公开(公告)号：US20230178600A1

公开(公告)日：2023-06-08

申请号：US17663463

申请日：2022-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Han Chuang ,  Zhi-Chang Lin ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Chien Ning Yao ,  Kai-Lin Chuang ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/0665 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. The semiconductor device structure includes a first bottom layer formed adjacent to the first nanostructures, and a first insulating layer formed over the first bottom layer. The semiconductor device structure includes a first source/drain (S/D) structure formed over the first insulating layer, and the first insulating layer is in direct contact with one of the first nanostructures.

公开(公告)号：US11664278B2

公开(公告)日：2023-05-30

申请号：US16935830

申请日：2020-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chi Chuang ,  Li-Zhen Yu ,  Yi-Hsun Chiu ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768

CPC classification number: H01L21/823431 ,  H01L21/76816 ,  H01L21/823437 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate; a metal gate structure disposed over a channel region of the semiconductor fin; a first interlayer dielectric (ILD) layer disposed over a source/drain (S/D) region next to the channel region of the semiconductor fin; and a first conductive feature including a first conductive portion disposed on the metal gate structure and a second conductive portion disposed on the first ILD layer, wherein a top surface of the first conductive portion is below a top surface of the second conductive portion, a first sidewall of the first conductive portion connects a lower portion of a first sidewall of the second conductive portion.