公开(公告)号：US20190221515A1

公开(公告)日：2019-07-18

申请号：US15872589

申请日：2018-01-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sipeng Gu ,  Jianwei Peng ,  Xusheng Wu ,  Yi Qi ,  Jeffrey Chee

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768

Abstract: Structures that include a metal-insulator-metal (MIM) capacitor and methods for fabricating a structure that includes a MIM capacitor. The MIM capacitor includes a first electrode, a second electrode, and a third electrode. A conductive via is arranged in a via opening extending in a vertical direction through at least the first electrode. The first electrode has a surface arranged inside the via opening in a plane transverse to the vertical direction, and the conductive via contacts the first electrode over an area of the surface.

公开(公告)号：US20190221473A1

公开(公告)日：2019-07-18

申请号：US16364465

申请日：2019-03-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Frank W. Mont ,  Errol Todd Ryan

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/76813 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53257 ,  H01L23/53295

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to skip via structures and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer with one or more wiring structures, located above the first wiring layer; a skip via with metallization, which passes through upper wiring levels including the second wiring layer and which makes contact with the one or more wiring structures of the first wiring layer; and a via structure which comprises a protective material and contacts at least one of the one or more wiring structures at the upper wiring level.

公开(公告)号：US20190219930A1

公开(公告)日：2019-07-18

申请号：US15869150

申请日：2018-01-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dongyue Yang ,  Xintuo Dai ,  Dongsuk Park ,  Minghao Tang ,  Md Motasim Bellah ,  Pavan Kumar Chinthamanipeta Sripadarao ,  Cheuk Wun Wong

IPC: G03F7/20 ,  G03F9/00

Abstract: Two pairs of alignment targets (one aligned, one misaligned by a bias distance) are formed on different masks to produce a first pair of conjugated interference patterns. Other pairs of alignment targets are also formed on the masks to produce a second pair of conjugated interference patterns that are inverted the first. Misalignment of the dark and light regions of the first interference patterns and the second interference patterns in both pairs of conjugated interference patterns is determined when patterns formed using the masks are overlaid. A magnification factor (of the interference pattern misalignment to the target misalignment) is calculated as a ratio of the difference of misalignment of the relatively dark and relatively light regions in the pairs of interference patterns, over twice the bias distance. The interference pattern misalignment is divided by the magnification factor to produce a self-referenced and self-calibrated target misalignment amount, which is then output.

公开(公告)号：US10355104B2

公开(公告)日：2019-07-16

申请号：US15795833

申请日：2017-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Sang Woo Lim ,  Kyung-Bum Koo ,  Alina Vinslava ,  Pei Zhao ,  Zhenyu Hu ,  Hsien-Ching Lo ,  Joseph F. Shepard, Jr. ,  Shesh Mani Pandey

IPC: H01L21/02 ,  H01L21/84 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/08

Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region beneath a top surface of a semiconductor fin. The semiconductor fin is etched with an anisotropic etching process to form a cavity having a sidewall with a planar section extending vertically toward the top surface of the semiconductor fin and adjacent to the channel region in the semiconductor fin. The semiconductor fin is then etched with an isotropic etching process that widens the cavity at the top surface while preserving verticality of the planar section.

公开(公告)号：US10355020B2

公开(公告)日：2019-07-16

申请号：US15180860

申请日：2016-06-13

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L27/12 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  G06N3/04 ,  G10L15/16 ,  H01L29/36

Abstract: Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET.

公开(公告)号：US20190214473A1

公开(公告)日：2019-07-11

申请号：US15867036

申请日：2018-01-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Balasubramanian Pranatharthiharan ,  Pietro Montanini ,  Julien Frougier

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/306 ,  H01L21/762 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L27/088 ,  H01L27/02

CPC classification number: H01L29/42392 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: Disclosed are methods for forming an integrated circuit with a nanowire-type field effect transistor and the resulting structure. A sacrificial gate is formed on a multi-layer fin. A sidewall spacer is formed with a gate section on the sacrificial gate and fin sections on exposed portions of the fin. Before or after removal of the exposed portions of the fin, the fins sections of the sidewall spacer are removed or reduced in size without exposing the sacrificial gate. Thus, the areas within which epitaxial source/drain regions are to be formed will not be bound by sidewall spacers. Furthermore, isolation material, which is deposited into these areas prior to epitaxial source/drain region formation and which is used to form isolation elements between the transistor gate and source/drain regions, can be removed without removing the isolation elements. Techniques are also disclosed for simultaneous formation of a nanosheet-type and/or fin-type field effect transistors.

公开(公告)号：US20190214469A1

公开(公告)日：2019-07-11

申请号：US15866855

申请日：2018-01-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bipul C. Paul ,  Ruilong Xie ,  Puneet Harischandra Suvarna

IPC: H01L29/417 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L23/48

CPC classification number: H01L29/41733 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/481 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0665

Abstract: Structures and circuits including multiple nanosheet field-effect transistors and methods of forming such structures and circuits. A complementary field-effect transistor includes a first nanosheet transistor with a source/drain region and a second nanosheet transistor with a source/drain region stacked over the source/drain region of the first nanosheet transistor. A contact extends vertically to connect the source/drain region of the first nanosheet transistor of the complementary field-effect transistor and the source/drain region of the second nanosheet transistor of the complementary field-effect transistor.

公开(公告)号：US10347745B2

公开(公告)日：2019-07-09

申请号：US15268751

申请日：2016-09-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Puneet Harischandra Suvarna ,  Steven J. Bentley ,  Daniel Chanemougame

IPC: H01L29/66 ,  H01L21/00 ,  H01L29/08 ,  H01L29/165

Abstract: One illustrative method disclosed herein includes, among other things, forming a vertically oriented channel semiconductor structure above a substrate, performing an epi deposition process to simultaneously form at least a portion of a bottom source/drain region and at least a portion of a top source/drain region during the epi deposition process and, after performing the epi deposition process, forming a gate structure around a portion of the vertically oriented channel semiconductor structure.

公开(公告)号：US10347622B2

公开(公告)日：2019-07-09

申请号：US15398946

申请日：2017-01-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： You Li ,  Manjunatha Prabu ,  Mujahid Muhammad ,  John B. Campi, Jr. ,  Robert J. Gauthier, Jr. ,  Souvick Mitra

IPC: H01L27/02 ,  H01L27/06 ,  H01L29/06 ,  H01L29/08 ,  H01L29/74

Abstract: Silicon-controlled rectifiers, electrostatic discharge circuits, and methods of fabricating a silicon-controlled rectifier for use in an electrostatic discharge circuit. A device structure for the silicon controlled rectifier includes a first well of a first conductivity type in a semiconductor layer, a second well of a second conductivity type in the semiconductor layer, a cathode coupled with the first well, and an anode coupled with the second well. First and second body contacts are coupled with the first well, and the first and second body contacts each have the first conductivity type. A triggering device may be coupled with the first body contact.

公开(公告)号：US20190206787A1

公开(公告)日：2019-07-04

申请号：US15860171

申请日：2018-01-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume BOUCHE ,  Lars W. LIEBMANN

IPC: H01L23/522 ,  H01L23/538 ,  H01L21/28

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to interrupted small block shape structures (e.g., cut metal lines forming cell boundaries) and methods of manufacture. The structure includes: a plurality of wiring lines with cuts that form a cell boundary; and at least one wiring line extending beyond the cell boundary and which is continuous from cell to cell.