公开(公告)号：US20170162565A1

公开(公告)日：2017-06-08

申请号：US15179992

申请日：2016-06-11

Applicant: International Business Machines Corporation ,  GlobalFoundries,Inc.

Inventor： Balasubramanian Pranatharthiharan ,  Hui Zang

IPC: H01L27/088 ,  H01L29/16 ,  H01L29/06 ,  H01L27/11

CPC classification number: H01L27/1104 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/3043 ,  H01L21/324 ,  H01L21/76 ,  H01L21/76224 ,  H01L21/8221 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/1116 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a set of fin structures having a set of fin ends at a respective vertical surface of a fin structure and is separated by a set of trenches from other fin structures. Each of the fin structures has a top surface which is higher than a top surface of a dielectric material in the set of trenches. A set of dielectric blocks is disposed at the set of fin ends, the dielectric blocks having a top surface level with or above the top surfaces of the fin structures which inhibit excessive epitaxial growth at the fin ends.

公开(公告)号：US09570615B2

公开(公告)日：2017-02-14

申请号：US14924925

申请日：2015-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/283 ,  H01L21/02 ,  H01L29/417 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/45 ,  H01L29/49 ,  H01L21/768

CPC classification number: H01L29/7851 ,  H01L21/02057 ,  H01L21/02112 ,  H01L21/283 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823418 ,  H01L29/0653 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A process for fabrication of semiconductor devices, particularly FinFETs, having a low contact horizontal resistance and a resulting device are provided. Embodiments include: providing a substrate having source and drain regions separated by a gate region; forming a gate electrode having a first length on the gate region; forming an epitaxy layer on the source and drain regions; forming a contact layer having a second length, longer than the first length, at least partially on the epitaxy layer; and forming an oxide layer on top and side surfaces of the contact layer for at least the first length.

Abstract translation: 提供了具有低接触水平电阻的半导体器件，特别是FinFET的制造工艺和所得到的器件。 实施例包括：提供具有由栅极区域分隔的源极和漏极区域的衬底; 在所述栅极区上形成具有第一长度的栅电极; 在源极和漏极区上形成外延层; 在所述外延层上至少部分地形成具有比所述第一长度长的第二长度的接触层; 以及在所述接触层的顶表面和侧表面上形成至少第一长度的氧化物层。

公开(公告)号：US20170025526A1

公开(公告)日：2017-01-26

申请号：US15183390

申请日：2016-06-15

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Jin Cho ,  MiaoMiao Wang ,  Hui Zang

IPC: H01L29/78 ,  H01L21/324 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/513 ,  H01L21/28026 ,  H01L21/324 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET). The method includes forming at least one fin, and forming a dielectric layer over at least a portion of the at least one fin. The method further includes forming a work function layer over at least a portion of the dielectric layer. The method further includes forming a source region or a drain region adjacent the at least one fin, and performing an anneal operation, wherein the anneal operation anneals the dielectric layer and either the source region or the drain region, and wherein the work function layer provides a protection function to the at least a portion of the dielectric layer during the anneal operation.

Abstract translation: 实施例涉及一种形成鳍型场效应晶体管（FinFET）的部分的方法。 该方法包括形成至少一个翅片，并且在至少一个翅片的至少一部分上形成电介质层。 该方法还包括在电介质层的至少一部分上形成功函数层。 所述方法还包括形成与所述至少一个鳍片相邻的源极区域或漏极区域，以及执行退火操作，其中所述退火操作使所述电介质层和所述源极区域或所述漏极区域退火，并且其中所述功函数层提供 在退火操作期间到介电层的至少一部分的保护功能。

公开(公告)号：US09536991B1

公开(公告)日：2017-01-03

申请号：US15067435

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Jerome Ciavatti ,  Min-hwa Chi

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/762

CPC classification number: H01L29/6681 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653

Abstract: A method of forming a single diffusion break includes patterning a fin hardmask disposed over a substrate. First and second fin arrays separated by an isolation region are etched into the substrate from the patterned fin hardmask. Any remaining fin hardmask being self-aligned with the fins. A first dielectric fill material is disposed and planarized over the arrays to expose top surfaces of the remaining fin hardmask. A second dielectric strip is formed over the first dielectric fill material to cover the isolation region and end portions of the remaining fin hardmask. Any exposed portions of the remaining fin hardmask are anisotropically etched away. The end portions of the remaining fin hardmask form base extensions of a base for a single diffusion break (SDB) in the isolation region. The first dielectric fill material and second dielectric strip are etched to complete formation of the base for the single diffusion break.

Abstract translation: 形成单个扩散断裂的方法包括图案化设置在基板上的散热片硬掩模。 由分离区隔开的第一和第二鳍状阵列从图案化的翅片硬掩模中蚀刻到基底中。 任何剩余的散热片硬掩模与翅片自对准。 第一介电填充材料在阵列上布置和平坦化以暴露剩余的散热片硬掩模的顶表面。 在第一介电填充材料上形成第二介质条以覆盖剩余的散热片硬掩模的隔离区域和端部。 剩余散热片硬掩模的任何暴露部分被各向异性地蚀刻掉。 剩余散热片硬掩模的端部形成用于隔离区域中的单个扩散断裂（SDB）的基部的基部延伸部。 蚀刻第一介电填充材料和第二介电条以完成单扩散断裂的基底的形成。

公开(公告)号：US20160365450A1

公开(公告)日：2016-12-15

申请号：US15208121

申请日：2016-07-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hyun-Jin Cho ,  Tenko Yamashita ,  Hui Zang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/423 ,  H01L27/092

CPC classification number: H01L29/512 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

公开(公告)号：US20160365346A1

公开(公告)日：2016-12-15

申请号：US14735984

申请日：2015-06-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hyun-Jin Cho ,  Tenko Yamashita ,  Hui Zang

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/512 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

Abstract translation: 一种形成用于半导体器件的栅极结构的方法，包括在存在于鳍状结构上的置换栅极结构的侧壁上形成第一间隔物，其中第一间隔物的上表面偏离替换栅极结构的上表面 并且在所述第一间隔物和所述替换栅极结构的所述暴露表面上形成至少第二间隔物。 该方法还可以包括用相邻的第一间隔件之间的第一空间中具有第一宽度部分的功能栅极结构代替替换栅极结构，以及在相邻的第二间隔物之间​​的第二空间中具有第二宽度的第二宽度部分，其中第二 宽度大于第一宽度。

公开(公告)号：US09496280B1

公开(公告)日：2016-11-15

申请号：US14700748

申请日：2015-04-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bingwu Liu ,  Xusheng Wu

IPC: H01L21/76 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/73 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/0684 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/0623 ,  H01L27/1207 ,  H01L29/0847 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/66568 ,  H01L29/732 ,  H01L29/7371 ,  H01L29/78

Abstract: A method can include epitaxially growing epitaxial growth material within a logic region of a semiconductor structure. A method can include performing simultaneously with the growing epitaxial growth within an analog region of the semiconductor structure. A method can include performing epitaxial growth to form an epitaxial growth formation that defines an electrode of an analog device within an analog region of the semiconductor structure, wherein the performing includes using a first surface and a second surface as seed surfaces.

Abstract translation: 一种方法可以包括在半导体结构的逻辑区域内外延生长外延生长材料。 一种方法可以包括与半导体结构的模拟区域内的增长的外延生长同时执行。 一种方法可以包括进行外延生长以形成限定半导体结构的模拟区域内的模拟器件的电极的外延生长结构，其中执行包括使用第一表面和第二表面作为晶种表面。

公开(公告)号：US09431396B2

公开(公告)日：2016-08-30

申请号：US14609564

申请日：2015-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bingwu Liu

IPC: H01L21/76 ,  H01L29/78 ,  H01L27/088 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/3213 ,  H01L21/02 ,  H01L27/02 ,  H01L21/28 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L27/0886 ,  H01L21/0217 ,  H01L21/28035 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0207 ,  H01L29/1083 ,  H01L29/41758 ,  H01L29/66545

Abstract: Methods of forming a SDB with a partial or complete insulator structure formed over the SDB and resulting devices are provided. Embodiments include forming a SDB with a first width in a substrate; forming a first metal gate in an ILD on top of the SDB, with a second width larger than the first width; forming second and third metal gates in the ILD on the substrate on opposite sides of the first metal gate, the second and third metal gates laterally separated from the first metal gate; forming a photoresist over the second and third gates; removing the first metal gate down to the SDB, forming a cavity; removing the photoresist; and filling the cavity with an insulator layer.

Abstract translation: 提供了形成在SDB上形成的部分或完全绝缘体结构的SDB和所得到的器件的方法。 实施例包括在衬底中形成具有第一宽度的SDB; 在所述SDB顶部的ILD中形成第一金属栅极，第二宽度大于所述第一宽度; 在第一金属栅极的相对侧上的衬底上的ILD中形成第二和第三金属栅极，第二和第三金属栅极与第一金属栅极横向分离; 在第二和第三栅极上形成光致抗蚀剂; 将第一金属栅极移到SDB上，形成空腔; 去除光致抗蚀剂; 并用绝缘体层填充空腔。

公开(公告)号：US20150364595A1

公开(公告)日：2015-12-17

申请号：US14731876

申请日：2015-06-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bingwu Liu ,  Hui Zang

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66818

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin protection layer around a fin, forming a sacrificial gate electrode above a section of the fin protection layer, forming at least one sidewall spacer adjacent the sacrificial gate electrode, removing the sacrificial gate electrode to define a gate cavity that exposes a portion of the fin protection layer, oxidizing at least the exposed portion of the fin protection layer to thereby form an oxidized portion of the fin protection layer, and removing the oxidized portion of the fin protection layer so as to thereby expose a surface of the fin within the gate cavity.

Abstract translation: 本文公开的一种说明性方法包括在鳍周围形成翅片保护层，在翅片保护层的一部分上形成牺牲栅电极，形成邻近牺牲栅电极的至少一个侧壁间隔物，去除牺牲栅极 电极，以限定露出所述鳍片保护层的一部分的栅极腔，至少氧化所述鳍片保护层的暴露部分，从而形成所述鳍片保护层的氧化部分，以及去除所述鳍片保护层的氧化部分，从而 从而使得在门腔内的翅片的表面露出。

公开(公告)号：US20150340470A1

公开(公告)日：2015-11-26

申请号：US14286144

申请日：2014-05-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang

IPC: H01L29/66 ,  H01L29/423

CPC classification number: H01L29/66795 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/78696

Abstract: One method includes forming trenches that define a fin structure including a first layer of a first semiconductor material and a second layer of a second semiconductor material positioned above a substrate, performing at least one etching process that exposes opposing end surfaces of the first and second layers, performing at least one recess etching process that removes end portions of the first layer and defines a cavity on opposite ends of the first layer, performing an epitaxial deposition process that fills each of the cavities with a support structure including a third semiconductor material, and performing an etching process to selectively remove remaining portions of the recessed first layer relative to the second layer and the support structures, the end portions of the second layer and the support structures defining pillars on opposite ends of the fin structure.

Abstract translation: 一种方法包括形成限定翅片结构的沟槽，所述鳍结构包括位于衬底上方的第一半导体材料的第一层和第二半导体材料的第二层，执行暴露第一和第二层的相对端面的至少一个蚀刻工艺 执行去除第一层的端部并限定第一层的相对端上的空腔的至少一个凹陷蚀刻工艺，执行利用包括第三半导体材料的支撑结构填充每个空腔的外延沉积工艺，以及 执行蚀刻工艺以相对于第二层和支撑结构选择性地去除凹陷的第一层的剩余部分，第二层的端部和支撑结构在翅片结构的相对端上限定支柱。