公开(公告)号：US20200152518A1

公开(公告)日：2020-05-14

申请号：US16185675

申请日：2018-11-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Chanro Park ,  Laertis Economikos

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L21/768 ,  H01L29/40

Abstract: Methods of forming cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include cross-coupling contacts. A dielectric cap is formed over a gate structure and a sidewall spacer adjacent to a sidewall of the gate structure. A portion of the dielectric cap is removed from over the sidewall spacer and the gate structure to expose a first portion of the gate electrode of the gate structure at a top surface of the gate structure. The sidewall spacer is then recessed relative to the gate structure to expose a portion of the gate dielectric layer at the sidewall of the gate structure, which is removed to expose a second portion of the gate electrode of the gate structure. A cross-coupling contact is formed that connects the first and second portions of the gate electrode of the gate structure with an epitaxial semiconductor layer adjacent to the sidewall spacer.

公开(公告)号：US10651291B2

公开(公告)日：2020-05-12

申请号：US15680467

申请日：2017-08-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Julien Frougier ,  Ruilong Xie

IPC: H01L29/20 ,  H01L29/16 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L21/223 ,  H01L21/311 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/786

Abstract: Structures for a nanosheet field-effect transistor and methods for forming a structure for a nanosheet field-effect transistor. A body feature is formed that includes a sacrificial layer arranged vertically between the first and second nanosheet channel layers. The sacrificial layer is laterally recessed at a sidewall of the body feature to expose respective portions of the first and second nanosheet channel layers. A sacrificial spacer is formed by oxidizing a portion of the sacrificial layer at the sidewall of the body feature. Sections of a semiconductor material are epitaxially grown on the exposed portions of the first and second nanosheet channel layers to narrow a gap vertically separating the first and second nanosheet channel layers. The sacrificial spacer is removed to form a cavity between the sections of the semiconductor material and the sacrificial layer. A dielectric spacer is conformally deposited in the cavity.

公开(公告)号：US20200135723A1

公开(公告)日：2020-04-30

申请号：US16170117

申请日：2018-10-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Haiting Wang ,  Chung Foong Tan ,  Guowei Xu ,  Ruilong Xie ,  Scott H. Beasor ,  Liu Jiang

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L29/49 ,  H01L21/8234

Abstract: A FinFET structure having reduced effective capacitance and including a substrate having at least two fins thereon laterally spaced from one another, a metal gate over fin tops of the fins and between sidewalls of upper portions of the fins, source/drain regions in each fin on opposing sides of the metal gate, and a dielectric bar within the metal gate located between the sidewalls of the upper portions of the fins, the dielectric bar being laterally spaced away from the sidewalls of the upper portions of the fins within the metal gate.

公开(公告)号：US20200111798A1

公开(公告)日：2020-04-09

申请号：US16152454

申请日：2018-10-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bipul C. Paul ,  Ruilong Xie

IPC: H01L27/11 ,  H01L23/528 ,  H01L21/768

Abstract: Disclosed are structures with a complementary field effect transistor (CFET) and a buried metal interconnect that electrically connects a source/drain region of a lower-level transistor of the CFET with another device. The structure can include a memory cell with first and second CFETs, where each CFET includes a pull-up transistor stacked on and having a common gate with a pull-down transistor and each pull-down transistor has a common source/drain region with a pass-gate transistor. The metal interconnect connects a lower-level source/drain region of the first CFET (i.e., the common source/drain region of first pass-gate and pull-up transistors) to the common gate of the second CFET (i.e., to the common gate of second pull-down and pull-up transistors). Formation methods include forming an interconnect placeholder during lower-level source/drain region formation. After upper-level source/drain regions and replacement metal gates are formed, the interconnect placeholder is exposed, removed and replaced with a metal interconnect.

公开(公告)号：US10600914B2

公开(公告)日：2020-03-24

申请号：US15869541

申请日：2018-01-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wei Zhao ,  Ming Hao Tang ,  Haiting Wang ,  Rui Chen ,  Yuping Ren ,  Hui Zang ,  Scott H. Beasor ,  Ruilong Xie

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/265 ,  H01L21/28 ,  H01L21/3105 ,  H01L27/11 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

Abstract: A method of forming isolation pillars for a gate structure, the method including: providing a preliminary structure including a substrate having a plurality of fins thereon, an STI formed between adjacent fins, an upper surface of the STIs extending higher than an upper surface of the fins, and a hardmask over the upper surface of the fins and between adjacent STIs; forming a first trench in a first selected STI and between adjacent fins in a gate region, and forming a second trench in a second selected STI and between adjacent fins in a TS region; and filling the first and second trenches with an isolation fill thereby forming a first isolation pillar in the gate region and a second isolation pillar in the TS region, the first and second isolation pillars extending below the upper surface of the STIs.

公开(公告)号：US10593593B2

公开(公告)日：2020-03-17

申请号：US16047470

申请日：2018-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vimal Kamineni ,  Ruilong Xie ,  Mark Raymond

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/82 ,  H01L29/417 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66

Abstract: Methods comprising forming a cobalt formation on an active feature of a semiconductor device, wherein the semiconductor device comprises an inactive feature above the cobalt formation; forming a cap on the cobalt formation; removing at least a portion of the inactive feature, wherein the cobalt formation is substantially not removed; forming a dielectric material above the cap; and forming a first contact to the cobalt formation. Systems configured to implement the methods. Semiconductor devices produced by the methods.

公开(公告)号：US10566248B1

公开(公告)日：2020-02-18

申请号：US16047044

申请日：2018-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Ruilong Xie ,  Chanro Park ,  Guillaume Bouche

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/06

Abstract: A method includes forming an isolation pillar between first and second active nanostructures for adjacent FETs. When a first WFM surrounding the second active nanostructure is removed as part of a WFM patterning process, creating a discontinuity in the first metal. The pillar or the discontinuity in the first metal on the part of the pillar prevent the etching from reaching and removing the first WFM on the first active nanostructure. The isolation pillar creates a gate cut isolation in a selected gate region, and can be shortened in another gate region to allow for gate sharing between adjacent FETs.

公开(公告)号：US20200052106A1

公开(公告)日：2020-02-13

申请号：US16101162

申请日：2018-08-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Laertis Economikos ,  Hui Zang ,  Ruilong Xie ,  Neal Makela ,  Pei Liu ,  Jiehui Shu ,  Chih-chiang Chang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/28

Abstract: At least one method, apparatus, and system providing semiconductor devices comprising a first gate having a first width and comprising a first work function metal (WFM); a first liner disposed over the first WFM; a first gate metal having a first height; and a first pinch-off spacer over the first WFM, the first liner, and the first gate metal to above the first height; and a second gate having a second width greater than the first width, and comprising a second WFM; a second liner disposed over the second WFM; a second gate metal having substantially the first height; and a first conformal spacer over the second WFM and the second liner.

公开(公告)号：US10559686B2

公开(公告)日：2020-02-11

申请号：US16018970

申请日：2018-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Hui Zang ,  Steven R. Soss

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/06 ,  H01L29/66 ,  H01L29/08

Abstract: Methods of making a vertical FinFET device having an electrical path over a gate contact landing, and the resulting device including a substrate having a bottom S/D layer thereover and fins extending vertically therefrom; a bottom spacer layer over the bottom S/D layer; a HKMG layer over the bottom spacer layer; a top spacer layer over the HKMG layer; a top S/D layer on top of each fin; top S/D contacts formed over the top S/D layer; an upper ILD layer present in spaces around the top S/D contacts; an isolation dielectric within a portion of a recess of top S/D contacts located above adjacent fins; a gate contact landing within a remaining portion of the recess; a gate contact extending vertically from a bottom surface of the gate contact landing and contacting a portion of the HKMG layer; and an electrical path over at least the gate contact landing.

公开(公告)号：US20190341468A1

公开(公告)日：2019-11-07

申请号：US15971043

申请日：2018-05-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Laertis Economikos ,  Ruilong Xie

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/3213 ,  H01L21/28

Abstract: A method includes forming a semiconductor device including a plurality of fins formed above a substrate, an isolation structure positioned between the plurality of fins, a plurality of sacrificial gate structures defining gate cavities, and a first dielectric material positioned between the sacrificial gate structures. A gate cut structure is formed in a first gate cavity. A trim etch process is performed to reduce a width of the gate cut structure. Replacement gate structures are formed in the gate cavities after performing the trim etch process. A first replacement gate structure in the first gate cavity is segmented by the gate cut structure.