公开(公告)号：US20080251498A1

公开(公告)日：2008-10-16

申请号：US11852203

申请日：2007-09-07

Applicant: Yi-Chan Chen

Inventor： Yi-Chan Chen

IPC: B44C1/22

CPC classification number: H01L45/1233 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1675

Abstract: A method for forming a memory device is disclosed. A dielectric layer is formed on a substrate. A Sn doped phase change layer is formed on the dielectric layer. A patterned mask layer is formed on the Sn doped phase change layer. The Sn doped phase change layer is etched by an etchant comprising fluorine-based etchant added with chlorine using the patterned mask layer as a mask to pattern the Sn doped phase change layer. An electrode is formed, electrically connecting the patterned Sn doped phase change layer.

Abstract translation: 公开了一种用于形成存储器件的方法。 在基板上形成电介质层。 在电介质层上形成Sn掺杂相变层。 在Sn掺杂相变层上形成图案化掩模层。 使用图案化掩模层作为掩模，通过包含添加有氯的氟基蚀刻剂的蚀刻剂来蚀刻Sn掺杂相变层以图案化Sn掺杂相变层。 形成电极，电连接图案化的Sn掺杂相变层。

公开(公告)号：US07435645B2

公开(公告)日：2008-10-14

申请号：US11164060

申请日：2005-11-09

Applicant: Jung-Wu Chien

Inventor： Jung-Wu Chien

IPC: H01L21/336

CPC classification number: H01L27/10864 ,  H01L27/10841 ,  H01L29/66181

Abstract: A dynamic random access memory (DRAM) includes a substrate, an active device and a deep trench capacitor. A trench and a deep trench are formed in the substrate. The active device is disposed on the substrate. The active device includes a gate structure and a doped region. The gate structure is disposed on the substrate and fills the trench. The doped region is disposed in the substrate at a first side of the gate structure. The deep trench capacitor is disposed in the deep trench of the substrate at a second side of the gate, and the second side is opposite to the first side. In addition, an upper electrode of the deep trench capacitor is adjacent to the bottom of the trench.

Abstract translation: 动态随机存取存储器（DRAM）包括衬底，有源器件和深沟槽电容器。 在衬底中形成沟槽和深沟槽。 有源器件设置在衬底上。 有源器件包括栅极结构和掺杂区域。 栅极结构设置在衬底上并填充沟槽。 掺杂区域设置在栅极结构的第一侧的衬底中。 深沟槽电容器设置在栅极的第二侧的衬底的深沟槽中，第二侧与第一侧相对。 此外，深沟槽电容器的上电极与沟槽的底部相邻。

公开(公告)号：US20080213968A1

公开(公告)日：2008-09-04

申请号：US11766308

申请日：2007-06-21

Applicant: Cheng-Che Lee ,  Hui-Ling Chuang ,  Hsing-Wu Yeh

Inventor： Cheng-Che Lee ,  Hui-Ling Chuang ,  Hsing-Wu Yeh

IPC: H01L21/20

CPC classification number: H01L28/91 ,  H01L27/0207 ,  H01L27/10852

Abstract: A method for fabricating a capacitor includes firstly providing a substrate. A doped first dielectric layer and an undoped second dielectric layer are then formed on the substrate sequentially. Next, many trenches are formed in the first and the second dielectric layers. Afterwards, an ion implantation process is performed in the largest space between the adjacent trenches to form an ion-implanted region in a portion of the second dielectric layer in upper parts of the trenches. A wet etching process is then performed to remove a portion of the second dielectric layer in the ion-implanted region and a portion of the first dielectric layer at bottoms of the trenches. Thereafter, a first conductive layer and a capacitor dielectric layer are formed sequentially on surfaces of the trenches. Finally, a second conductive layer is formed in the trenches.

Abstract translation: 制造电容器的方法包括首先提供衬底。 然后依次在衬底上形成掺杂的第一介电层和未掺杂的第二介电层。 接下来，在第一和第二电介质层中形成许多沟槽。 然后，在相邻沟槽之间的最大空间中进行离子注入工艺，以在沟槽的上部的第二电介质层的一部分中形成离子注入区。 然后执行湿式蚀刻工艺以去除离子注入区域中的第二介电层的一部分和在沟槽底部的第一电介质层的一部分。 此后，在沟槽的表面上依次形成第一导电层和电容器电介质层。 最后，在沟槽中形成第二导电层。

公开(公告)号：US20080203374A1

公开(公告)日：2008-08-28

申请号：US12010885

申请日：2008-01-30

Applicant: Yen Chuo ,  Hong-Hui Hsu

Inventor： Yen Chuo ,  Hong-Hui Hsu

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  H01L45/06 ,  H01L45/124 ,  H01L45/144 ,  H01L45/1691

Abstract: A phase-change memory is provided. The phase-change memory comprises a substrate. A first electrode is formed on the substrate. A circular or linear phase-change layer is electrically connected to the first electrode. A second electrode formed on the phase-change layer and electrically connected to the phase-change layer, wherein at least one of the first electrode and the second electrode comprises phase-change material.

Abstract translation: 提供了相变存储器。 相变存储器包括衬底。 在基板上形成第一电极。 圆形或线性相变层电连接到第一电极。 形成在所述相变层上并与所述相变层电连接的第二电极，其中所述第一电极和所述第二电极中的至少一个包括相变材料。

公开(公告)号：US20080186762A1

公开(公告)日：2008-08-07

申请号：US12010761

申请日：2008-01-29

Applicant: Yen Chuo ,  Frederick T. Chen

Inventor： Yen Chuo ,  Frederick T. Chen

IPC: G11C11/00

CPC classification number: G11C13/0004 ,  G11C2213/56 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683

Abstract: A phase-change memory is provided. The phase-change memory comprises first and second electrodes, wherein the first and second electrodes comprise phase-change material. A conductive path is formed between the first and second electrodes and electrically connects the first and second electrodes, wherein the conductive path comprises an embedded metal layer and a phase-change layer resulting in current from the first electrode to the second electrode or from the second electrode to the first electrode passing through the embedded metal layer and the phase change layer.

Abstract translation: 提供了相变存储器。 相变存储器包括第一和第二电极，其中第一和第二电极包括相变材料。 导电路径形成在第一和第二电极之间并且电连接第一和第二电极，其中导电路径包括嵌入金属层和相变层，其导致从第一电极到第二电极或第二电极的电流 电极通过嵌入金属层和相变层的第一电极。

公开(公告)号：US20080179585A1

公开(公告)日：2008-07-31

申请号：US11956282

申请日：2007-12-13

Applicant: Hong-Hui Hsu

Inventor： Hong-Hui Hsu

IPC: H01L47/00 ,  C23C16/44

CPC classification number: H01L45/1675 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148

Abstract: A phase change memory device is provided. The phase change memory device includes a substrate. A metal plug is disposed on the substrate and a phase change material film is disposed on the metal plug, wherein the metal plug is electrically connected to the phase change material film. A heating electrode is disposed on the phase change material film, wherein the heating electrode is electrically connected to the phase change material film. A conductive layer is disposed on the heating electrode.

Abstract translation: 提供了相变存储器件。 相变存储器件包括衬底。 金属插头设置在基板上，相变材料膜设置在金属插头上，其中金属插头与相变材料膜电连接。 加热电极设置在相变材料膜上，其中加热电极与相变材料膜电连接。 导电层设置在加热电极上。

公开(公告)号：US20080137462A1

公开(公告)日：2008-06-12

申请号：US12020352

申请日：2008-01-25

Applicant: Jon Allan Faue ,  Steve Eaton ,  Michael Murray

Inventor： Jon Allan Faue ,  Steve Eaton ,  Michael Murray

IPC: G11C7/00

CPC classification number: G11C7/1078 ,  G11C7/1072 ,  G11C7/1093 ,  G11C7/1096

Abstract: A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge of an input data strobe, the last two bits are transmitted over the bus, which eliminates the need for the precise counting of input data strobe pulses. The data bus circuit is compatible with both DDR1 and DDR2 operating modes.

Abstract translation: 用于集成电路存储器的数据总线电路包括用于将存储器与I / O块连接的每个I / O焊盘的4位总线，但每个I / O仅使用两位用于写入。 使用四位每个I / O焊盘进行读取。 在输入数据选通的每个下降沿，最后两位通过总线发送，这样就不需要精确计数输入数据选通脉冲。 数据总线电路兼容DDR1和DDR2工作模式。

公开(公告)号：US20080128892A1

公开(公告)日：2008-06-05

申请号：US11566160

申请日：2006-12-01

Applicant: Hsiao Che Wu ,  Yu Min Tsai ,  Wen Li Tsai

Inventor： Hsiao Che Wu ,  Yu Min Tsai ,  Wen Li Tsai

IPC: H01L23/48

CPC classification number: H01L24/11 ,  H01L23/522 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/585 ,  H01L24/03 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00

Abstract: An integrated circuit device comprises a substrate, a stack structure including circuit structure having conductive lines positioned on the substrate, a reinforcement structure including at least one supporting member positioned on the substrate and a roof covering the circuit structure and the supporting member and at least one bonding pad positioned on the roof and electrically connected to the conductive lines. A method for preparing an integrated circuit device comprises forming a stack structure including circuit structure having conductive lines on a substrate, forming a reinforcement structure including at least one supporting member on the substrate and a roof covering the supporting member and the circuit structure and forming at least one bonding pad on the roof and electrically connecting to the conductive lines.

Abstract translation: 集成电路装置包括基板，包括具有位于基板上的导线的电路结构的堆叠结构，包括位于基板上的至少一个支撑构件和覆盖电路结构和支撑构件的顶板的加强结构以及至少一个 接合垫定位在屋顶上并电连接到导电线。 一种集成电路器件的制造方法，其特征在于，在基板上形成具有导线的电路结构的堆叠结构，形成包括所述基板上的至少一个支撑部件的加强结构以及覆盖所述支撑部件和所述电路结构的屋顶， 至少一个焊盘在屋顶上并且电连接到导电线。

公开(公告)号：US20080124885A1

公开(公告)日：2008-05-29

申请号：US11624219

申请日：2007-01-18

Applicant: Tsung-De Lin ,  Cheng-Che Lee

Inventor： Tsung-De Lin ,  Cheng-Che Lee

IPC: H01L21/768 ,  H01L21/62

CPC classification number: H01L28/91 ,  H01L27/10852

Abstract: A method of fabricating an electrode of a capacitor is provided. A substrate is provided and a dielectric layer is then formed thereon. After that, one multilayer mask is formed on the dielectric layer to expose a portion of the dielectric layer, wherein the multilayer mask consists of at least two layers of materials having different etching rates respectively. The exposed dielectric layer is removed to form a trench, and then the dielectric layer is over-etched, so as to widen the inside diameter of the trench. Thereafter, a conductive layer is formed on the substrate, and thus the multilayer mask and a surface of the trench are covered with the conductive layer. The conductive layer except that in the trench is then removed so as to form the electrode of the capacitor. Therefore, it can prevent the conductive layer from generating more loss.

Abstract translation: 提供制造电容器的电极的方法。 提供衬底，然后在其上形成电介质层。 之后，在电介质层上形成一个多层掩模，以暴露介电层的一部分，其中多层掩模由分别具有不同蚀刻速率的至少两层材料构成。 去除暴露的电介质层以形成沟槽，然后对电介质层进行过蚀刻，以扩大沟槽的内径。 此后，在基板上形成导电层，因此多层掩模和沟槽的表面被导电层覆盖。 然后除去在沟槽中的导电层，以便形成电容器的电极。 因此，可以防止导电层产生更多的损耗。

公开(公告)号：US20080121984A1

公开(公告)日：2008-05-29

申请号：US12010827

申请日：2008-01-30

Applicant: Jason Chen ,  Chien Kang Kao

Inventor： Jason Chen ,  Chien Kang Kao

IPC: H01L29/788

CPC classification number: H01L29/42352 ,  H01L29/045 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/7923

Abstract: A flash memory structure comprises a silicon substrate having at least one concave structure, two doped regions positioned in the semiconductor substrate and at two sides of the concave structure, at least one carrier-trapping region positioned in the concave structure, and a conductive layer positioned above the concave structure. The concave structure comprises two grooves having a U-shaped or V-shaped profile. The grooves have an inclined plane with (111) orientation and a bottom plane with (100) orientation of the silicon substrate. The carrier-trapping region comprises a dielectric stack positioned in the concave structure, wherein the dielectric stack comprises a first oxide layer positioned on the surface of the silicon substrate, a nitride block positioned on the surface of the first oxide layer and in the concave structure, and a second oxide layer covering the first oxide layer and the nitride block.

Abstract translation: 闪速存储器结构包括具有至少一个凹结构的硅衬底，位于半导体衬底中的两个掺杂区域和位于凹构造两侧的至少一个载流子捕获区域，以及定位在凹形结构中的导电层 在凹形结构之上。 凹形结构包括具有U形或V形轮廓的两个凹槽。 凹槽具有具有（111）取向的倾斜平面和具有（100）硅衬底取向的底平面。 载体捕获区域包括位于凹形结构中的电介质堆叠，其中介电堆叠包括位于硅衬底的表面上的第一氧化物层，位于第一氧化物层表面上的氮化物块和凹形结构 以及覆盖第一氧化物层和氮化物块的第二氧化物层。