公开(公告)号：US20150235859A1

公开(公告)日：2015-08-20

申请号：US14616004

申请日：2015-02-06

Applicant: Robert Bosch GmbH

Inventor： Simon ARMBRUSTER ,  Frank FISCHER ,  Johannes BAADER ,  Rainer STRAUB

IPC: H01L21/311 ,  H01L21/02

CPC classification number: H01L21/311 ,  B81C1/00801 ,  B81C2201/014 ,  H01L21/02118 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0228

Abstract: A method for structuring a layered structure, for example, of a micromechanical component, from two semiconductor layers between which an insulating and/or etch stop layer is situated includes forming a first etching mask on a first side of the first semiconductor layer, carrying out a first etching step, starting from a first outer side, for structuring the first semiconductor layer, forming a second etching mask on a second side of the second semiconductor layer, and carrying out a second etching step, starting from the second outer side, for structuring the second semiconductor layer. After carrying out the first etching step and prior to carrying out the second etching step, at least one etching protection material is deposited on at least one trench wall of at least one first trench, which is etched in the first etching step.

Abstract translation: 用于从两个半导体层构成诸如微机械部件的分层结构的绝缘和/或蚀刻停止层的方法包括在第一半导体层的第一侧上形成第一蚀刻掩模，执行 第一蚀刻步骤，从第一外侧开始，用于构造第一半导体层，在第二半导体层的第二侧上形成第二蚀刻掩模，并且执行第二蚀刻步骤，从第二外侧开始，用于 构造第二半导体层。 在执行第一蚀刻步骤之后并且在进行第二蚀刻步骤之前，至少一个蚀刻保护材料沉积在至少一个第一沟槽的至少一个沟槽壁上，该第一沟槽在第一蚀刻步骤中被蚀刻。

公开(公告)号：US09096427B2

公开(公告)日：2015-08-04

申请号：US14286175

申请日：2014-05-23

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT

Inventor： Sofiane Ben Mbarek ,  Sophie Giroud ,  Frederic-Xavier Gaillard

IPC: H01L21/00 ,  B81C1/00

CPC classification number: B81C1/00531 ,  B81B2203/0118 ,  B81C1/0015 ,  B81C1/00539 ,  B81C2201/0114 ,  B81C2201/0115 ,  B81C2201/014 ,  B81C2201/019 ,  B81C2203/036

Abstract: Method for making at least one first suspended part of a microelectronic or nanoelectronic structure from a monolithic part of a first substrate, the method comprising the following steps: make a first etching with a first given depth in the monolithic substrate to define the suspended part, deposit a protective layer on at least the side edges of the first etching, make a second etching with a second depth in the first etching, make a physicochemical treatment of at least part of the zone located under the suspended structure so as to modify it, and release the suspended part by removal of the physicochemically treated part.

Abstract translation: 用于从第一衬底的整体部分制造微电子或纳米电子结构的至少一个第一悬浮部分的方法，所述方法包括以下步骤：在所述整体式衬底中进行第一给定深度的第一蚀刻以限定所述悬浮部分， 在第一蚀刻的至少侧边缘上沉积保护层，在第一蚀刻中进行具有第二深度的第二蚀刻，对位于悬挂结构下方的区域的至少一部分进行物理化学处理，以进行改性， 并通过去除物理化学处理的部分释放悬浮的部分。

公开(公告)号：US09064950B2

公开(公告)日：2015-06-23

申请号：US14135506

申请日：2013-12-19

Applicant: XINTEC INC.

Inventor： Chia-Lun Tsai ,  Chia-Ming Cheng ,  Long-Sheng Yeou

IPC: H01L21/78 ,  B81C1/00

CPC classification number: H01L21/78 ,  B81B2207/07 ,  B81B2207/098 ,  B81C1/00825 ,  B81C2201/014 ,  B81C2201/053 ,  B81C2203/0118

Abstract: An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a chip protection layer or an additional etching stop layer to cover conducting pads to prevent dicing residue from damaging or scratching the conducting pads. According to another embodiment, a chip protection layer, an additional etching stop layer formed thereon, or a metal etching stop layer level with conducting pads or combinations thereof may be used when etching an intermetal dielectric layer at a structural etching region and a silicon substrate to form an opening for subsequent semiconductor manufacturing processes.

Abstract translation: 本发明的实施例涉及一种芯片封装及其制造方法，其包括芯片保护层或附加的蚀刻停止层，以覆盖导电焊盘，以防止切割残留物损坏或划伤导电焊盘。 根据另一个实施例，当蚀刻结构蚀刻区域和硅衬底上的金属间电介质层时，可以使用芯片保护层，其上形成的附加蚀刻停止层或具有导电焊盘或其组合的金属蚀刻停止层， 形成随后的半导体制造工艺的开口。

公开(公告)号：US20150158723A1

公开(公告)日：2015-06-11

申请号：US14624008

申请日：2015-02-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kai-Chih Liang ,  Chia-Hua Chu ,  Te-Hao Lee ,  Jiou-Kang Lee ,  Chung-Hsien Lin

IPC: B81B7/00

CPC classification number: B81C1/00515 ,  B81B7/0006 ,  B81B7/0077 ,  B81B2201/0235 ,  B81B2203/0315 ,  B81B2207/07 ,  B81B2207/095 ,  B81B2207/096 ,  B81C1/00293 ,  B81C1/00301 ,  B81C2201/0132 ,  B81C2201/014 ,  B81C2203/0109 ,  B81C2203/0118 ,  B81C2203/0145 ,  B81C2203/035 ,  H01L2224/11

Abstract: A microelectromechanical system (MEMS) device may include a MEMS structure over a first substrate. The MEMS structure comprises a movable element. Depositing a first conductive material over the first substrate and etching trenches in a second substrate. Filling the trenches with a second conductive material and depositing a third conductive material over the second conductive material and the second substrate. Bonding the first substrate and the second substrate and thinning a backside of the second substrate which exposes the second conductive material in the trenches.

Abstract translation: 微机电系统（MEMS）装置可以包括在第一基板上的MEMS结构。 MEMS结构包括可移动元件。 在第一衬底上沉积第一导电材料并蚀刻第二衬底中的沟槽。 用第二导电材料填充沟槽并在第二导电材料和第二衬底上沉积第三导电材料。 将第一基板和第二基板接合并使第二基板的背面变薄，从而在沟槽中露出第二导电材料。

公开(公告)号：US08932893B2

公开(公告)日：2015-01-13

申请号：US13868125

申请日：2013-04-23

Applicant: Matthieu Lagouge

Inventor： Matthieu Lagouge

IPC: H01L29/84 ,  H01L21/00 ,  B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00801 ,  B81B2201/0235 ,  B81B2203/0307 ,  B81C2201/014 ,  B81C2203/036

Abstract: A method of fabricating a microelectromechanical (MEMS) device includes bonding a transducer wafer to a substrate wafer along a bond interface. An unpatterned transducer layer included within the transducer wafer is patterned. A release etch process is then performed during which a sacrificial layer is exposed to a selected release etchant to remove at a least a portion of the sacrificial layer through the openings in the patterned transducer layer. A release etch stop layer is formed between the sacrificial layer and the bond interface prior to exposing the sacrificial layer to the release etchant. The release etch stop layer prevents the ingress of the selected release etchant into the region of the MEMS device containing the bond interface during the release etch process.

Abstract translation: 一种制造微机电（MEMS）装置的方法包括沿着键合界面将换能器晶片连接到衬底晶片。 包含在换能器晶片内的未图案化的换能器层被图案化。 然后执行释放蚀刻工艺，在此期间，牺牲层暴露于所选择的释放蚀刻剂，以通过图案化的换能器层中的开口在牺牲层的至少一部分上移除。 在将牺牲层暴露于释放蚀刻剂之前，在牺牲层和接合界面之间形成释放蚀刻停止层。 释放蚀刻停止层在释放蚀刻工艺期间防止所选择的剥离蚀刻剂进入包含结合界面的MEMS器件的区域中。

公开(公告)号：US20140357006A1

公开(公告)日：2014-12-04

申请号：US14286175

申请日：2014-05-23

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT

Inventor： Sofiane BEN MBAREK ,  Sophie Giroud ,  Frederic-Xavier Gaillard

IPC: B81C1/00

CPC classification number: B81C1/00531 ,  B81B2203/0118 ,  B81C1/0015 ,  B81C1/00539 ,  B81C2201/0114 ,  B81C2201/0115 ,  B81C2201/014 ,  B81C2201/019 ,  B81C2203/036

Abstract: Method for making at least one first suspended part of a microelectronic or nanoelectronic structure from a monolithic part of a first substrate, the method comprising the following steps: make a first etching with a first given depth in the monolithic substrate to define the suspended part, deposit a protective layer on at least the side edges of the first etching, make a second etching with a second depth in the first etching, make a physicochemical treatment of at least part of the zone located under the suspended structure so as to modify it, and release the suspended part by removal of the physicochemically treated part.

Abstract translation: 用于从第一衬底的整体部分制造微电子或纳米电子结构的至少一个第一悬浮部分的方法，所述方法包括以下步骤：在所述整体式衬底中进行第一给定深度的第一蚀刻以限定所述悬浮部分， 在第一蚀刻的至少侧边缘上沉积保护层，在第一蚀刻中进行具有第二深度的第二蚀刻，对位于悬挂结构下方的区域的至少一部分进行物理化学处理，以进行改性， 并通过去除物理化学处理的部分释放悬浮的部分。

公开(公告)号：US20140342557A1

公开(公告)日：2014-11-20

申请号：US14370529

申请日：2013-01-03

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT

Inventor： Bernard Diem

IPC: B81C1/00

CPC classification number: B81C1/00619 ,  B81B2203/033 ,  B81B2203/0392 ,  B81C1/00103 ,  B81C1/00531 ,  B81C1/00539 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/014 ,  H01L21/3083

Abstract: A method for etching a desired complex pattern in a first face of a substrate, including: simultaneous etching of at least a first and a second sub-pattern through the first face of the substrate, the etched sub-patterns being separated by at least one separating wall, a width of the first sub-pattern being greater than a width of the second sub-pattern at the first face, and a depth of the first sub-pattern being greater than a depth of the second sub-pattern in a direction perpendicular to the said first face; and removing or eliminating the separating wall to expose the desired complex pattern.

Abstract translation: 一种在衬底的第一面中蚀刻期望的复合图案的方法，包括：通过衬底的第一面同时蚀刻至少第一和第二子图案，蚀刻的子图案被至少一个 分隔壁，所述第一子图案的宽度大于所述第一面处的所述第二子图案的宽度，并且所述第一子图案的深度大于所述第二子图案的方向上的深度 垂直于所述第一面; 以及去除或除去分离壁以暴露所需的复杂图案。

公开(公告)号：US08887569B2

公开(公告)日：2014-11-18

申请号：US13177485

申请日：2011-07-06

Applicant: Jong Woon Kim ,  Won Kyu Jeung

Inventor： Jong Woon Kim ,  Won Kyu Jeung

IPC: G01P15/02 ,  G01P15/09 ,  G01P15/18 ,  G01C19/56 ,  C23F1/02 ,  G01P15/08

CPC classification number: B81C1/00158 ,  B81B3/0062 ,  B81B3/007 ,  B81B2201/0235 ,  B81B2203/053 ,  B81C1/00484 ,  B81C1/00531 ,  B81C1/00539 ,  B81C1/00571 ,  B81C2201/01 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/014 ,  C09K13/00 ,  C09K13/08 ,  G01C19/56 ,  G01P15/0802 ,  G01P15/0922 ,  G01P15/18 ,  G01P2015/084 ,  G01P2015/0871

Abstract: Disclosed herein an inertial sensor and a method of manufacturing the same. An inertial sensor 100 according to a preferred embodiment of the present invention is configured to include a plate-shaped membrane 110, a mass body 120 that includes an adhesive part 123 disposed under a central portion 113 of the membrane 110 and provided at the central portion thereof and a patterning part 125 provided at an outer side of the adhesive part 123 and patterned to vertically penetrate therethrough, and a first adhesive layer 130 that is formed between the membrane 110 and the adhesive part 123 and is provided at an inner side of the patterning part 125. An area of the first adhesive layer 130 is narrow by isotropic etching using the patterning part 125 as a mask, thereby making it possible to improve sensitivity of the inertial sensor 100.

Abstract translation: 本文公开了一种惯性传感器及其制造方法。 根据本发明的优选实施例的惯性传感器100被配置为包括板状膜110，质量体120，其包括设置在膜110的中心部分113下方并设置在中心部分处的粘合部123 以及设置在粘合部123的外侧并被图案化以垂直贯穿其中的图案形成部分125，以及形成在膜110和粘合部123之间的第一粘合层130，并且设置在第一粘合层130的内侧 图形部分125.通过使用图案形成部分125作为掩模的各向同性蚀刻，第一粘合剂层130的区域变窄，从而可以提高惯性传感器100的灵敏度。

公开(公告)号：US20140292430A1

公开(公告)日：2014-10-02

申请号：US14219694

申请日：2014-03-19

Applicant: SEIKO EPSON CORPORATION

Inventor： Takahiko YOSHIZAWA

IPC: H01L23/04 ,  H01L23/00 ,  H03B5/30 ,  H01L21/768

CPC classification number: H03B5/30 ,  B81C1/00246 ,  B81C1/00801 ,  B81C2201/014 ,  B81C2203/0742 ,  B81C2203/0764 ,  H01L21/76802 ,  H03B5/32

Abstract: An electronic device according to an aspect of the invention include: a substrate; an underlayer having an opening and being formed on the substrate; a functional element provided on the underlayer; and a surrounding wall forming a cavity that accommodates the functional element, at least a part of the surrounding wall being disposed in the opening.

Abstract translation: 根据本发明的一个方面的电子设备包括：基板; 具有开口并形成在所述基板上的底层; 设置在底层上的功能元件; 以及形成容纳所述功能元件的空腔的周壁，所述周围壁的至少一部分设置在所述开口中。

公开(公告)号：US20140231937A1

公开(公告)日：2014-08-21

申请号：US14262437

申请日：2014-04-25

Applicant: STMicroelectronics S.r.l.

Inventor： Stefano Losa ,  Raffaella Pezzuto ,  Roberto Campedelli ,  Matteo Perletti ,  Luigi Esposito ,  Mikel Azpeitia Urquia

IPC: B81C1/00 ,  B81B7/00

CPC classification number: H01L21/02178 ,  B81B7/0032 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C1/00595 ,  B81C1/00801 ,  B81C2201/014 ,  B81C2201/053 ,  H01L21/0228

Abstract: A method for manufacturing a protective layer for protecting an intermediate structural layer against etching with hydrofluoric acid, the intermediate structural layer being made of a material that can be etched or damaged by hydrofluoric acid, the method comprising the steps of: forming a first layer of aluminium oxide, by atomic layer deposition, on the intermediate structural layer; performing a thermal crystallization process on the first layer of aluminium oxide, forming a first intermediate protective layer; forming a second layer of aluminium oxide, by atomic layer deposition, above the first intermediate protective layer; and performing a thermal crystallization process on the second layer of aluminium oxide, forming a second intermediate protective layer and thereby completing the formation of the protective layer. The method for forming the protective layer can be used, for example, during the manufacturing steps of an inertial sensor such as a gyroscope or an accelerometer.

Abstract translation: 一种用于制造用于保护中间结构层以防止用氢氟酸蚀刻的保护层的方法，所述中间结构层由可被氢氟酸蚀刻或损坏的材料制成，所述方法包括以下步骤：形成第一层 氧化铝，通过原子层沉积在中间结构层上; 在第一氧化铝层上进行热结晶处理，形成第一中间保护层; 通过原子层沉积在第一中间保护层之上形成第二层氧化铝; 并在第二氧化铝层上进行热结晶处理，形成第二中间保护层，从而完成保护层的形成。 形成保护层的方法可以用于例如陀螺仪或加速度计等惯性传感器的制造步骤。