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公开(公告)号:US12199085B2
公开(公告)日:2025-01-14
申请号:US17716934
申请日:2022-04-08
Applicant: Intel Corporation
Inventor: Robert L. Sankman , Sairam Agraharam , Shengquan Ou , Thomas J De Bonis , Todd Spencer , Yang Sun , Guotao Wang
IPC: H01L25/00 , H01L21/56 , H01L23/00 , H01L23/538 , H01L25/18
Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.
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公开(公告)号:US12199063B2
公开(公告)日:2025-01-14
申请号:US18403545
申请日:2024-01-03
Applicant: Intel Corporation
Inventor: Shawna M. Liff , Adel A. Elsherbini , Johanna M. Swan , Arun Chandrasekhar
IPC: H01L25/065 , H01L23/00 , H01L25/00 , H01L25/18
Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
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223.
公开(公告)号:US12198535B2
公开(公告)日:2025-01-14
申请号:US17955384
申请日:2022-09-28
Applicant: Intel Corporation
Inventor: N. V. S. Kumar Srighakollapu , Ankur Mishra , Sreejith Satheesakurup , Saunak Bhalsod
IPC: G06F1/32 , G06F1/3212 , G06F3/02 , G08B5/36
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that implement an off-screen indication of battery charge in mobile platforms. In an example, the apparatus includes a keyboard, an interface circuitry, and a processor circuitry. The example processor circuitry to instantiate remaining state of charge (RSOC) controller circuitry to detect a battery charge level display event on a mobile device, the mobile device in a pre-boot state. The example processor circuitry additionally to instantiate fuel gauge circuitry to determine a charge level of a battery of the mobile device and keyboard display circuitry to, after the battery charge level display event, cause a display of the charge level of the battery in the pre-boot state with ones of backlights of a second ones keys on the keyboard.
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公开(公告)号:US12198221B2
公开(公告)日:2025-01-14
申请号:US18436494
申请日:2024-02-08
Applicant: Intel Corporation
Inventor: Prasoonkumar Surti , Narayan Srinivasa , Feng Chen , Joydeep Ray , Ben J. Ashbaugh , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Balaji Vembu , Tsung-Han Lin , Kamal Sinha , Rajkishore Barik , Sara S. Baghsorkhi , Justin E. Gottschlich , Altug Koker , Nadathur Rajagopalan Satish , Farshad Akhbari , Dukhwan Kim , Wenyin Fu , Travis T. Schluessler , Josh B. Mastronarde , Linda L Hurd , John H. Feit , Jeffery S. Boles , Adam T. Lake , Karthik Vaidyanathan , Devan Burke , Subramaniam Maiyuran , Abhishek R. Appu
Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.
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公开(公告)号:US12197601B2
公开(公告)日:2025-01-14
申请号:US17560193
申请日:2021-12-22
Applicant: Intel Corporation
Inventor: Ren Wang , Sameh Gobriel , Somnath Paul , Yipeng Wang , Priya Autee , Abhirupa Layek , Shaman Narayana , Edwin Verplanke , Mrittika Ganguli , Jr-Shian Tsai , Anton Sorokin , Suvadeep Banerjee , Abhijit Davare , Desmond Kirkpatrick , Rajesh M. Sankaran , Jaykant B. Timbadiya , Sriram Kabisthalam Muthukumar , Narayan Ranganathan , Nalini Murari , Brinda Ganesh , Nilesh Jain
Abstract: Examples described herein relate to offload circuitry comprising one or more compute engines that are configurable to perform a workload offloaded from a process executed by a processor based on a descriptor particular to the workload. In some examples, the offload circuitry is configurable to perform the workload, among multiple different workloads. In some examples, the multiple different workloads include one or more of: data transformation (DT) for data format conversion, Locality Sensitive Hashing (LSH) for neural network (NN), similarity search, sparse general matrix-matrix multiplication (SpGEMM) acceleration of hash based sparse matrix multiplication, data encode, data decode, or embedding lookup.
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公开(公告)号:US12197357B2
公开(公告)日:2025-01-14
申请号:US17556853
申请日:2021-12-20
Applicant: Intel Corporation
Inventor: Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC: G06F13/22 , G06F1/3287 , G06F8/71 , G06F8/77 , G06F9/30 , G06F9/445 , G06F9/46 , G06F11/10 , G06F12/0806 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F13/40 , G06F13/42 , H04L9/06 , H04L49/15 , G06F8/73 , H04L12/46 , H04L45/74
Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
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公开(公告)号:US20250016567A1
公开(公告)日:2025-01-09
申请号:US18793322
申请日:2024-08-02
Applicant: Intel Corporation
Inventor: Markus Dominik Mueck
Abstract: The present disclosure is related to reconfigurable radio equipment and edge computing, and in particular, to technologies for cyber security and radio equipment supporting certain features ensuring protection from fraud, and testing interfaces related to reconfigurable radio equipment. Other embodiments may be described and/or claimed.
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公开(公告)号:US20250015974A1
公开(公告)日:2025-01-09
申请号:US18887066
申请日:2024-09-17
Applicant: Intel Corporation
Inventor: Robert VAUGHN , John HANSEN
IPC: H04L9/08
Abstract: Provided is a method for detecting an Artificial Intelligence (AI) agent of an application in a network. In this method, the varieties of a plurality of outputs of the application may be determined, where the outputs are respectively corresponding to a plurality of identical inputs provided to the application. Furthermore, the method may detect, based on the varieties of the plurality of outputs, the AI agent of the application, wherein the AI agent comprises an AI model providing AI-based resource information to the application to generate the plurality of outputs.
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229.
公开(公告)号:US20250014967A1
公开(公告)日:2025-01-09
申请号:US18893576
申请日:2024-09-23
Applicant: Intel Corporation
Inventor: Kyle Jordan Arrington , Prabhakar Subrahmanyam , Steven Adam Klein , Kelly Porter Lofgreen , Joseph Blane Petrini
IPC: H01L23/473 , H01L23/40 , H01L23/42 , H01R12/85 , H01R13/52
Abstract: Systems, apparatus, articles of manufacture, and methods to improve thermal dissipation and mechanical loading of integrated circuit packages are disclosed. An example apparatus includes: a socket to receive an integrated circuit package; and a plate to apply a load on the integrated circuit package towards the socket. The plate includes an internal channel to carry a coolant through the plate. The liquid coolant is to facilitate cooling of the integrated circuit package.
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公开(公告)号:US20250013420A1
公开(公告)日:2025-01-09
申请号:US18895818
申请日:2024-09-25
Applicant: Intel Corporation
Inventor: Sean J. W. Lawrence
Abstract: Systems and methods for controlling flexible displays are disclosed herein. An example apparatus includes interface circuitry; machine-readable instructions; and at least one processor circuit to at least one of instantiate or execute the machine-readable instructions to determine a distance of a user relative to a display screen based on outputs of a sensor, the sensor in communication with one or more of the at least one processor circuit; determine a curvature radius of the display screen based on the user distance; and cause an actuator to adjust a curvature of the display screen based on the curvature radius.
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