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    Method of forming split gate memory cells with 5 volt logic devices
    226.
    发明授权
    Method of forming split gate memory cells with 5 volt logic devices 有权
    用5伏逻辑器件形成分离栅极存储单元的方法

    公开(公告)号：US09570592B2

    公开(公告)日：2017-02-14

    申请号：US15164796

    申请日：2016-05-25

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Nhan Do ,  Vipin Tiwari

    IPC: H01L21/28 ,  H01L21/265 ,  H01L21/768 ,  H01L29/66 ,  H01L27/115

    CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L27/11529 ,  H01L29/66484 ,  H01L29/7885

    Abstract: A method of forming a memory device on a semiconductor substrate having a memory region (with floating and control gates), a first logic region (with first logic gates) and a second logic region (with second logic gates). A first implantation forms the source regions adjacent the floating gates in the memory region, and the source and drain regions adjacent the first logic gates in the first logic region. A second implantation forms the source and drain regions adjacent the second logic gates in the second logic region. A third implantation forms the drain regions adjacent the control gates in the memory region, and enhances the source region in the memory region and the source/drain regions in the first logic region. A fourth implantation enhances the source/drain regions in the second logic region.

    Abstract translation: 在具有存储区域（具有浮动和控制栅极）的第一逻辑区域（具有第一逻辑门）和第二逻辑区域（具有第二逻辑门）的半导体衬底上形成存储器件的方法。 第一注入形成与存储区域中的浮置栅极相邻的源极区域，以及与第一逻辑区域中的第一逻辑门极相邻的源区域和漏极区域。 第二注入形成与第二逻辑区域中的第二逻辑门相邻的源区和漏区。 第三注入形成与存储器区域中的控制栅极相邻的漏极区域，并且增强第一逻辑区域中的存储区域和源极/漏极区域中的源极区域。 第四次注入增强了第二逻辑区域中的源极/漏极区域。

    Method of forming a self-aligned stack gate structure for use in a non-volatile memory array
    227.
    发明授权
    Method of forming a self-aligned stack gate structure for use in a non-volatile memory array 有权
    形成用于非易失性存储器阵列的自对准堆叠栅极结构的方法

    公开(公告)号：US09570581B2

    公开(公告)日：2017-02-14

    申请号：US15091202

    申请日：2016-04-05

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Willem-Jan Toren ,  Xian Liu ,  Gerhard Metzger-Brueckl ,  Nhan Do ,  Stephan Wege ,  Nadia Miridi ,  Chieng-Sheng Su ,  Cecile Bernardi ,  Liz Cuevas ,  Florence Guyot ,  Yueh-Hsin Chen ,  Henry Om'mani ,  Mandana Tadayoni

    IPC: H01L29/788 ,  H01L29/66 ,  H01L21/28 ,  H01L27/115 ,  H01L21/762

    CPC classification number: H01L29/66545 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76283 ,  H01L27/11521 ,  H01L27/11568

    Abstract: A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.

    Abstract translation: 用于非易失性存储器阵列的堆叠栅极结构具有半导体衬底，该半导体衬底具有多个基本上平行的间隔开的有源区，每个有源区具有沿第一方向的轴。 在垂直于第一方向的第二方向上，第一绝缘材料位于每个堆叠栅极结构之间。 每个堆叠栅极结构在有源区域上具有第二绝缘材料，在第二绝缘材料上方的电荷保持栅极，电荷保持栅极上方的第三绝缘材料以及位于第三绝缘材料上的控制栅极的第一部分。 控制栅极的第二部分在控制栅极的第一部分之上，并且与第一部分相邻并且在第二方向上延伸。 第四绝缘材料位于控制栅极的第二部分之上。

    Method of making embedded memory device with silicon-on-insulator substrate
    228.
    发明授权
    Method of making embedded memory device with silicon-on-insulator substrate 有权
    使用绝缘体上硅衬底制造嵌入式存储器件的方法

    公开(公告)号：US09431407B2

    公开(公告)日：2016-08-30

    申请号：US14491596

    申请日：2014-09-19

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chien-Sheng Su ,  Hieu Van Tran ,  Mandana Tadayoni ,  Nhan Do ,  Jeng-Wei Yang

    IPC: H01L21/00 ,  H01L21/84 ,  H01L27/115 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L21/306 ,  H01L21/762 ,  H01L21/28 ,  H01L27/12

    CPC classification number: H01L27/11531 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/7624 ,  H01L27/11521 ,  H01L27/11534 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/66825

    Abstract: A method of forming a semiconductor device starts with a substrate of silicon, a first insulation layer on the silicon, and a silicon layer on the first insulation layer. The silicon layer and the insulation layer are removed just from a second substrate area. A second insulation layer is formed over the silicon layer in the substrate first area and over the silicon in the second substrate area. A first plurality of trenches is formed in the first substrate area that each extends through all the layers and into the silicon. A second plurality of trenches is formed in the second substrate area that each extends through the second insulation layer and into the silicon. An insulation material is formed in the first and second trenches. Logic devices are formed in the first substrate area, and memory cells are formed in the second substrate area.

    Abstract translation: 形成半导体器件的方法从硅衬底，硅上的第一绝缘层和第一绝缘层上的硅层开始。 仅从第二衬底区域去除硅层和绝缘层。 第二绝缘层形成在衬底第一区域中的硅层之上并且在第二衬底区域中的硅上方。 第一多个沟槽形成在第一衬底区域中，每个沟槽延伸穿过所有层并进入硅中。 第二多个沟槽形成在第二衬底区域中，每个沟槽延伸穿过第二绝缘层并进入硅中。 绝缘材料形成在第一和第二沟槽中。 逻辑器件形成在第一衬底区域中，并且存储器单元形成在第二衬底区域中。

    Non-volatile memory cells with enhanced channel region effective width, and method of making same
    230.
    发明授权
    Non-volatile memory cells with enhanced channel region effective width, and method of making same 有权
    具有增强的通道区域有效宽度的非易失性存储单元及其制造方法

    公开(公告)号：US09293359B2

    公开(公告)日：2016-03-22

    申请号：US14191625

    申请日：2014-02-27

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Nhan Do ,  Hieu Van Tran ,  Chien-Sheng Su ,  Prateep Tuntasood

    IPC: H01L29/788 ,  H01L21/762 ,  H01L29/66 ,  H01L27/115 ,  H01L21/28 ,  H01L29/423

    CPC classification number: H01L21/76224 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

    Abstract: A memory device array with spaced apart parallel isolation regions formed in a semiconductor substrate, with an active region between each pair of adjacent isolation regions. Each isolation region includes a trench formed into the substrate surface and an insulation material formed in the trench. Portions of a top surface of the insulation material are recessed below the surface of the substrate. Each active region includes a column of memory cells each having spaced apart first and second regions with a channel region therebetween, a floating gate over a first channel region portion, and a select gate over a second channel region portion. The select gates are formed as continuous word lines extending perpendicular to the isolation regions and each forming the select gates for one row of the memory cells. Portions of each word line extend down into the trenches and disposed laterally adjacent to sidewalls of the trenches.

    Abstract translation: 一种存储器件阵列，其具有形成在半导体衬底中的间隔开的平行隔离区域，在每对相邻隔离区域之间具有有源区域。 每个隔离区域包括形成在衬底表面中的沟槽和形成在沟槽中的绝缘材料。 绝缘材料的顶表面的部分凹陷在基底的表面下方。 每个有源区域包括一列存储单元，每个存储单元具有间隔开的第一和第二区域，其间具有通道区域，在第一沟道区域部分上的浮动栅极以及在第二沟道区域部分上的选择栅极。 选择栅极形成为垂直于隔离区域延伸的连续字线，并且每个形成用于一行存储器单元的选择栅极。 每个字线的一部分向下延伸到沟槽中并且横向设置成与沟槽的侧壁相邻。

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