公开(公告)号：US20160013205A1

公开(公告)日：2016-01-14

申请号：US14771025

申请日：2013-02-28

Applicant: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Maud VINET ,  Kangguo CHENG ,  Bruce DORIS ,  Laurent GRENOUILLET ,  Ali KHAKIFIROOZ ,  Yannick LE TIEC ,  Qing LIU

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L27/12 ,  H01L21/762 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/0653

Abstract: An integrated circuit, including: a first cell, including: FDSOI transistors; a UTBOX layer lying beneath the transistors; a first well lying beneath the insulator layer and beneath the transistors, the first well having a first type of doping; a first ground plane having a second type of doping, located beneath one of the transistors and between the insulator layer and the first well; a first STI separating the transistors and crossing the insulator layer; a first conductive element forming an electrical connection between the first well and the first ground plane, located under the first STI; a second cell including a second well; a second STI separating the cells, crossing the insulator layer and reaching the bottom of the first and second wells.

Abstract translation: 一种集成电路，包括：第一单元，包括：FDSOI晶体管; 位于晶体管下方的UTBOX层; 第一阱位于绝缘体层之下并位于晶体管下方，第一阱具有第一类掺杂; 具有第二类型掺杂的第一接地平面，位于所述晶体管中的一个之下且在所述绝缘体层和所述第一阱之间; 分离晶体管并与绝缘体层交叉的第一STI; 第一导电元件，其形成位于第一STI之下的第一阱和第一接地平面之间的电连接; 包括第二井的第二池; 分离所述电池的第二STI，穿过所述绝缘体层并到达所述第一和第二阱的底部。

公开(公告)号：US09230857B2

公开(公告)日：2016-01-05

申请号：US14522011

申请日：2014-10-23

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Lindsey H. Hall ,  Michael Hatzistergos ,  Ahmet S. Ozcan ,  Filippos Papadatos ,  Yiyi Wang

IPC: H01L21/768 ,  H01L21/3213 ,  H01L21/321

CPC classification number: H01L21/76877 ,  H01L21/32115 ,  H01L21/32135 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76871 ,  H01L21/76892

Abstract: A method of forming a semiconductor device is disclosed. The method including providing a substrate with at least one insulating layer disposed thereon, the at least one insulating layer including a trench; forming at least one liner layer on the at least one insulating layer; forming a nucleation layer on the at least one liner layer; forming a first metal film on a surface of the nucleation layer; etching the first metal film; and depositing a second metal film on the etched surface of the first metal film, the second metal film substantially forming an overburden above the trench.

公开(公告)号：US20150372107A1

公开(公告)日：2015-12-24

申请号：US14308014

申请日：2014-06-18

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh ,  Kejia Wang

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/31111 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods and structures associated with forming finFETs that have fin pitches less than 30 nm are described. A selective nitridation process may be used during spacer formation on the gate to enable finer fin pitch than could be achieved using traditional spacer deposition processes. The spacer formation may also allow precise control over formation of source and drain junctions.

Abstract translation: 描述了与形成翅片间距小于30nm的finFET相关联的方法和结构。 可以在栅极上的间隔物形成期间使用选择性氮化工艺，以使得能够使用传统间隔物沉积工艺可以获得更细的翅片间距。 间隔物形成还可以允许对源极和漏极结的形成的精确控制。

公开(公告)号：US20150364578A1

公开(公告)日：2015-12-17

申请号：US14307011

申请日：2014-06-17

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh ,  Xiuyu Cai ,  Kejia Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/20

CPC classification number: H01L29/66795 ,  H01L29/20 ,  H01L29/205 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: Methods and structures for forming a reduced resistance region of a finFET are described. According to some aspects, a dummy gate and first gate spacer may be formed above a fin comprising a first semiconductor composition. At least a portion of source and drain regions of the fin may be removed, and a second semiconductor composition may be formed in the source and drain regions in contact with the first semiconductor composition. A second gate spacer may be formed covering the first gate spacer. The methods may be used to form finFETs having reduced resistance at source and drain junctions.

Abstract translation: 描述了形成finFET的电阻减小区域的方法和结构。 根据一些方面，可以在包括第一半导体组合物的鳍片之上形成伪栅极和第一栅极间隔物。 可以去除鳍的源区和漏区的至少一部分，并且可以在与第一半导体组合物接触的源区和漏区中形成第二半导体组合物。 可以形成覆盖第一栅极间隔物的第二栅极间隔物。 该方法可用于形成在源极和漏极结处具有降低的电阻的finFET。

公开(公告)号：US09214429B2

公开(公告)日：2015-12-15

申请号：US14098346

申请日：2013-12-05

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Hsueh-Chung Chen ,  Lawrence A. Clevenger ,  Yann Mignot ,  Carl Radens ,  Richard Stephen Wise ,  Yannick Loquet ,  Yiheng Xu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76879 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect structure incorporates deep air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of a deep air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the deep air gap is used as an insulator and a means of reducing fringe capacitance between adjacent metal lines. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

Abstract translation: 在高性能集成电路中用作层间电介质的超低k电介质材料容易在结构上不稳定。 这种材料的杨氏模量降低，导致孔隙率，差的膜强度，开裂和空隙。 一种替代的双镶嵌互连结构将深空气隙结合到高模量介电材料中以维持结构稳定性，同时减小相邻纳米线之间的电容。 结合k = 1.0的深空气间隙补偿使用介电常数大于典型的超低k（ULK）介电值约2.2的介电常数的较高模量的膜。 使用含有深空气间隙的较高模量的膜作为绝缘体和减少相邻金属线之间的条纹电容的装置。 因此，两个相邻金属线之间的电介质层形成ULK /高模量介电双层。

公开(公告)号：US20150357983A1

公开(公告)日：2015-12-10

申请号：US14296914

申请日：2014-06-05

Applicant: STMICROELECTRONICS, INC.

Inventor： Davy Choi

IPC: H03G1/00 ,  H03F1/02 ,  H03F3/45

CPC classification number: H03G3/02 ,  H03F1/0205 ,  H03F1/26 ,  H03F3/3022 ,  H03F3/393 ,  H03F3/45 ,  H03F3/45094 ,  H03F3/45179 ,  H03F3/45475 ,  H03F2200/261 ,  H03F2203/45116 ,  H03F2203/45138 ,  H03F2203/45336 ,  H03G1/0035 ,  H03G1/02 ,  H03G3/3036 ,  H03M1/18

Abstract: An instrumentation amplifier includes first and second resistors for gain setting. The operational amplifiers within the instrumentation amplifier include selectively enabled current drive sources coupled to the amplifier output. The first and second resistors have variable resistances. A control circuit is configured to select the variable resistances of the first and second resistors to implement a fixed gain for the instrumentation amplifier and further selectively enable the current drive sources. The control circuit receives an indication of a downstream programmable gain (for example, from a downstream programmable gain amplifier). The variable resistances of the first and second resistors are selected to be scaled inversely with respect to the downstream programmable gain and the current drive sources are enabled proportionately with respect to the downstream programmable gain.

Abstract translation: 仪表放大器包括用于增益设定的第一和第二电阻器。 仪表放大器内的运算放大器包括耦合到放大器输出的有选择地使能的电流驱动源。 第一和第二电阻具有可变电阻。 控制电路被配置为选择第一和第二电阻器的可变电阻以实现仪器放大器的固定增益，并且进一步选择性地启用当前的驱动源。 控制电路接收下游可编程增益的指示（例如，从下游可编程增益放大器）。 第一和第二电阻器的可变电阻被选择为相对于下游可编程增益反相缩放，并且当前驱动源相对于下游可编程增益成比例地启用。

公开(公告)号：US20150357441A1

公开(公告)日：2015-12-10

申请号：US14300506

申请日：2014-06-10

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Kejia Wang ,  Chun-Chen Yeh

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/28114 ,  H01L21/32137 ,  H01L21/32139 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate, and a gate overlying the semiconductor fins. The gate has a tapered outer surface. A first pair of sidewall spacers is formed adjacent the gate an exposed tapered outer surface is also defined. Portions of the gate are removed at the exposed tapered outer surface to define a recess. A second pair of sidewall spacers is formed covering the first pair of sidewall spacers and the recess. Source/drain regions are formed on the semiconductor fins.

Abstract translation: 制造半导体器件的方法包括在衬底上形成横向间隔开的半导体鳍片，以及覆盖半导体鳍片的栅极。 门具有锥形外表面。 在栅极附近形成第一对侧壁间隔物，露出的锥形外表面也被限定。 在露出的锥形外表面上去除栅极的部分以限定凹部。 形成第二对侧壁间隔件，覆盖第一对侧壁间隔件和凹部。 源极/漏极区域形成在半导体鳍片上。

公开(公告)号：US20150357425A1

公开(公告)日：2015-12-10

申请号：US14297822

申请日：2014-06-06

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh ,  Xiuyu Cai ,  William J. Taylor

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823475 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.

Abstract translation: 在基板上形成集成电路晶体管。 衬底中的沟槽至少部分地与金属材料填充以形成埋在衬底中的源极（或漏极）接触。 衬底还包括与源极（或漏极）接触电连接的衬底中的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底可以是绝缘体上硅（SOI）或体积型。 埋入的源极（或漏极）接触器使用与源极（或漏极）和沟道区域在基底的相同水平处提供的接点，使得与源极（或漏极）区域的一侧电连接。

公开(公告)号：US20150349085A1

公开(公告)日：2015-12-03

申请号：US14288766

申请日：2014-05-28

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  Ruilong XIE ,  Xiuyu CAI ,  Chun-chen YEH

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers.

Abstract translation: 制造半导体器件的方法包括在衬底上形成横向间隔开的半导体鳍片。 在半导体鳍片的端部附近和相邻的半导体鳍片之间的空间内形成至少一个电介质层。 在半导体翅片的端部处邻近最外半导体翅片形成一对侧壁间隔物。 去除该对侧壁间隔物之间​​的至少一个电介质层和半导体翅片的端部。 源极/漏极区域形成在该对侧壁间隔物之间​​。

公开(公告)号：US20150348879A1

公开(公告)日：2015-12-03

申请号：US14293364

申请日：2014-06-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Jefferson TALLEDO

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/4825 ,  H01L23/3107 ,  H01L23/49517 ,  H01L23/4952 ,  H01L23/49537 ,  H01L23/49541 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/73265 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/8385 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A semiconductor device may include an IC, and lead frame contact areas adjacent the IC. Each lead frame contact area may have a lead opening. The semiconductor device may include bond wires, each bond wire coupling a respective lead frame contact area with the IC. The semiconductor device may include encapsulation material surrounding the IC, the lead frame contact areas, and the bond wires, and leads. Each lead may extend through a respective lead opening and outwardly from the encapsulation material.

Abstract translation: 半导体器件可以包括IC，以及与IC相邻的引线框架接触区域。 每个引线框接触区域可以具有引线开口。 半导体器件可以包括接合线，每个接合线将相应的引线框架接触区域与IC耦合。 半导体器件可以包括围绕IC的封装材料，引线框架接触区域和接合线以及引线。 每个引线可以延伸通过相应的引线开口并且从封装材料向外延伸。