公开(公告)号：US20240351865A1

公开(公告)日：2024-10-24

申请号：US18622059

申请日：2024-03-29

Applicant: Xintec Inc.

Inventor： Jiun-Yen LAI ,  Wei-Luen SUEN ,  Ming-Chung CHUNG ,  Chih-Wei LIU

IPC: B81C1/00

CPC classification number: B81C1/00825 ,  B81C2201/013 ,  B81C2201/0143 ,  B81C2201/0146 ,  B81C2201/0159

Abstract: A manufacturing method of a micro electro mechanical system (MEMS) device includes forming a buffer protection layer on a semiconductor structure, wherein the semiconductor structure includes a wafer, a MEMS membrane, and an isolation layer between the wafer and the MEMS membrane, and the buffer protection layer is located in a slit of the MEMS membrane and on a surface of the MEMS membrane facing away from the isolation layer; etching the wafer to form a cavity such that a portion of the isolation layer is exposed though the cavity; etching the portion of the isolation layer; and removing the buffer protection layer.

公开(公告)号：US20240304582A1

公开(公告)日：2024-09-12

申请号：US18431627

申请日：2024-02-02

Applicant: Xintec Inc.

Inventor： Wei-Ming CHIEN ,  Po-Han LEE ,  Tsang-Yu LIU

IPC: H01L23/00 ,  H01L23/498 ,  H05K1/18

CPC classification number: H01L24/16 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H05K1/181 ,  H01L2224/11424 ,  H01L2224/11464 ,  H01L2224/13155 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13664 ,  H01L2224/16225 ,  H01L2924/1431

Abstract: A circuit substrate in a chip package is provided. The circuit substrate includes first and second insulating layers covering opposite first and second surfaces of the semiconductor substrate, respectively. The circuit substrate also includes first and second pads disposed in the first and second insulating layers, respectively, and laterally separated from an opening that extends from the first surface to the second surface of the semiconductor substrate. The circuit substrate further includes first and second under bump metallization (UBM) layers disposed on the first and second pads, respectively. The first UBM layer has a surface protruding above the first insulating layer, and the second UBM layer extends from the second pad onto the second insulating layer, and is partially recessed into the second insulating layer to form a concave surface.

公开(公告)号：US11973095B2

公开(公告)日：2024-04-30

申请号：US17861011

申请日：2022-07-08

Applicant: XINTEC INC.

Inventor： Kuei-Wei Chen ,  Chia-Ming Cheng ,  Chia-Sheng Lin

IPC: H01L27/146

CPC classification number: H01L27/14618 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14687 ,  H01L27/14698 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1464

Abstract: A chip package including a substrate, a first conductive structure, and an electrical isolation structure is provided. The substrate has a first surface and a second surface opposite the first surface), and includes a first opening and a second opening surrounding the first opening. The substrate includes a sensor device adjacent to the first surface. A first conductive structure includes a first conductive portion in the first opening of the substrate, and a second conductive portion over the second surface of the substrate. An electrical isolation structure includes a first isolation portion in the second opening of the substrate, and a second isolation portion extending from the first isolation portion and between the second surface of the substrate and the second conductive portion. The first isolation portion surrounds the first conductive portion.

公开(公告)号：US11935859B2

公开(公告)日：2024-03-19

申请号：US17588185

申请日：2022-01-28

Applicant: XINTEC INC.

Inventor： Jiun-Yen Lai ,  Chia-Hsiang Chen

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L24/29 ,  H01L23/481 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L2224/29026

Abstract: A chip structure includes a first substrate, a second substrate, a conductive via, and a redistribution layer. The first substrate has a first inclined sidewall. The second substrate is located on a bottom surface of the first substrate, and has an upper portion and a lower portion. The lower portion extends from the upper portion. The upper portion is between the first substrate and the lower portion. The upper portion has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall. The conductive via is in the lower portion. The redistribution layer extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via.

公开(公告)号：US11749618B2

公开(公告)日：2023-09-05

申请号：US17980507

申请日：2022-11-03

Applicant: XINTEC INC.

Inventor： Chia-Ming Cheng ,  Shu-Ming Chang

IPC: H01L23/528 ,  H01L23/552 ,  H01L23/66 ,  H01L21/56 ,  H01L23/31 ,  H01L23/522

CPC classification number: H01L23/552 ,  H01L21/565 ,  H01L23/3135 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/66 ,  H01L2223/6605 ,  H01L2223/6677

Abstract: A chip package includes a first substrate, a second substrate, a first conductive layer, and a metal layer. The first substrate has a bottom surface and an inclined sidewall adjoining the bottom surface, and an obtuse angle is between the bottom surface and the inclined sidewall. The second substrate is over the first substrate and has a portion that laterally extends beyond the inclined sidewall of the first substrate. The first conductive layer is between the first substrate and the second substrate. The metal layer is on said portion of the second substrate, on the bottom surface and the inclined sidewall of the first substrate, and electrically connected to an end of the first conductive layer.

公开(公告)号：US20230238305A1

公开(公告)日：2023-07-27

申请号：US18157033

申请日：2023-01-19

Applicant: XINTEC INC.

Inventor： Ching-Ting PENG ,  Sheng-Hsiang FU ,  Hsin-Yi CHEN

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/784 ,  H01L21/304 ,  H01L21/308 ,  H01L21/683

CPC classification number: H01L23/481 ,  H01L24/05 ,  H01L24/03 ,  H01L24/32 ,  H01L21/784 ,  H01L21/304 ,  H01L21/3086 ,  H01L21/6835 ,  H01L2224/02381 ,  H01L2224/02317 ,  H01L2224/05073 ,  H01L2224/05575 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05567 ,  H01L2224/32225 ,  H01L2221/68372

Abstract: A chip package includes a semiconductor substrate, a conductive pad, an isolation layer, and a redistribution layer. The semiconductor substrate has a first surface, a second surface facing away from the first surface, a through hole through the first and second surfaces, and a recess in the first surface. The conductive pad is located on the second surface of the semiconductor substrate and in the through hole. The isolation layer is located on the second surface of the semiconductor substrate and surrounds the conductive pad. The redistribution layer is located on the first surface of the semiconductor substrate, and extends into the recess, and extends onto the conductive pad in the through hole.

公开(公告)号：US20230230933A1

公开(公告)日：2023-07-20

申请号：US18149029

申请日：2022-12-30

Applicant: XINTEC INC.

Inventor： Chia-Ming CHENG ,  Chaung-Lin LAI ,  Shu-Ming CHANG ,  Tsang-Yu LIU

IPC: H01L23/544 ,  H01L27/146

CPC classification number: H01L23/544 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2223/54433

Abstract: A chip package includes a sensing element, a dam layer, and a light transmissive cover. A surface of the sensing element has a sensing area and a conductive pad. The conductive pad is adjacent to an edge of the surface of the sensing element. The dam layer is located on the surface of the sensing element and surrounds the sensing area. The dam layer has a main portion and plural mark portions. The mark portions are respectively located in plural corners of the main portion, located in a sidewall of the main portion, respectively located on plural corners of the sensing element, respectively located on plural inner edges of the main portion, or respectively located on plural outer edges of the main portion. The light transmissive cover is located on the dam layer.

公开(公告)号：US11695199B2

公开(公告)日：2023-07-04

申请号：US17407068

申请日：2021-08-19

Applicant: XINTEC INC.

Inventor： Jiun-Yen Lai ,  Ming-Chung Chung ,  Wei-Luen Suen

IPC: H01Q1/38 ,  H01Q1/52 ,  H01Q23/00 ,  H01Q1/24

CPC classification number: H01Q1/38 ,  H01Q1/526 ,  H01Q1/243 ,  H01Q23/00

Abstract: An antenna device includes a first substrate, a second substrate, an antenna layer, and a redistribution layer. The first substrate has a first surface, a second surface opposite to the first surface, and an inclined sidewall adjoining the first and second surfaces. The second substrate is below the first substrate. The first surface of the first substrate faces toward the second substrate. The antenna layer is located on the first surface of the first substrate. The redistribution layer extends from the second surface of the first substrate to the second substrate along the inclined sidewall of the first substrate, and the redistribution layer has a first section in contact with an end of the antenna layer.

公开(公告)号：US20230081775A1

公开(公告)日：2023-03-16

申请号：US17895643

申请日：2022-08-25

Applicant: XINTEC INC.

Inventor： Hsin-Yi CHEN ,  Sheng-Hsiang FU ,  Ching Ting PENG ,  Ho Yin YIU

IPC: H01L23/552 ,  H01L23/498 ,  H01L21/48

Abstract: A chip package includes a semiconductor substrate, an interlayer dielectric (ILD) layer, a first metal shielding layer, and a redistribution layer. The semiconductor substrate has a first surface, a second surface facing away from the first surface, an inclined sidewall adjoining the first and second surfaces, and a through hole through the first and second surfaces. The ILD layer is located on the first surface of the semiconductor substrate, and a first conductive pad structure and a second conductive pad structure are disposed in the ILD layer. The first metal shielding layer is located on the ILD layer. A portion of the first metal shielding layer is located in the ILD layer and on the second conductive pad structure. The redistribution layer is located on the second surface of the semiconductor substrate, a wall surface of the through hole, and the first conductive pad structure.

公开(公告)号：US20220384373A1

公开(公告)日：2022-12-01

申请号：US17750228

申请日：2022-05-20

Applicant: XINTEC INC.

Inventor： Chieh CHAN ,  Yen-Chen LEE

IPC: H01L23/00 ,  H01L23/48

Abstract: A chip package includes a semiconductor structure and a redistribution layer. The semiconductor structure has a substrate, a first isolation layer, and a lower ground pad. The substrate has a top surface, a bottom surface opposite to the top surface, a through hole through the top surface and the bottom surface, and a sidewall surrounding the through hole. The first isolation layer is located on the top surface of the substrate, and the lower ground pad is located in the through hole. The redistribution layer extends from the bottom surface of the substrate to the lower ground pad along the sidewall. The redistribution layer covers the entire bottom surface of the substrate and electrically connects the lower ground pad.