公开(公告)号：US10998447B2

公开(公告)日：2021-05-04

申请号：US15451514

申请日：2017-03-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki ,  Kiyoshi Kato ,  Tomoaki Atsumi

IPC: G11C16/10 ,  H01L29/786 ,  G11C11/401 ,  G11C11/404 ,  G11C16/04 ,  H01L27/11517 ,  H01L27/11563 ,  H01L27/12 ,  H01L29/24

Abstract: A semiconductor device is provided in which the power consumption can be reduced by reducing the driving voltage and the on-state current can be increased in a period in which a transistor having an extremely low off-state current is brought into an electrically floating state. The semiconductor device comprises a memory cell, a first circuit, and a second circuit. The memory cell includes a first transistor. The first transistor includes a first semiconductor layer, a first gate electrode, and a first back gate electrode. The first gate electrode is connected to a word line. The first back gate electrode is connected to a back gate line. The first circuit supplies a signal for controlling the conduction state of the first transistor to the word line. The second circuit supplies a voltage for controlling the threshold voltage of the first transistor to the back gate line. The second circuit has a function of bringing the back gate line into an electrically floating state in a period in which a signal for controlling the conduction state of the first transistor is supplied to the word line.

公开(公告)号：US10811417B2

公开(公告)日：2020-10-20

申请号：US16558386

申请日：2019-09-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: H01L27/105 ,  H01L27/12 ,  H01L29/24 ,  H01L29/16 ,  G11C11/405 ,  G11C16/04 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/118 ,  H01L27/115 ,  H01L29/786 ,  H01L21/822 ,  H01L27/06 ,  H01L27/108 ,  H01L29/78

Abstract: An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

公开(公告)号：US10749033B2

公开(公告)日：2020-08-18

申请号：US14172072

申请日：2014-02-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiromichi Godo ,  Ryota Imahayashi ,  Kiyoshi Kato

IPC: H01L29/04 ,  H01L29/15 ,  H01L29/786 ,  H01L27/12 ,  H01L29/49 ,  H01L29/66

Abstract: Disclosed is a semiconductor device including: an insulating layer; a source electrode and a drain electrode embedded in the insulating layer; an oxide semiconductor layer in contact and over the insulating layer, the source electrode, and the drain electrode; a gate insulating layer over and covering the oxide semiconductor layer; and a gate electrode over the gate insulating layer, where the upper surfaces of the insulating layer, the source electrode, and the drain electrode exist coplanarly. The upper surface of the insulating layer, which is in contact with the oxide semiconductor layer, has a root-mean-square (RMS) roughness of 1 nm or less, and the difference in height between the upper surface of the insulating layer and the upper surface of the source electrode or the drain electrode is less than 5 nm. This structure contributes to the suppression of defects of the semiconductor device and enables their miniaturization.

公开(公告)号：US10693448B2

公开(公告)日：2020-06-23

申请号：US16362777

申请日：2019-03-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Yutaka Shionoiri ,  Tomoaki Atsumi ,  Takanori Matsuzaki

IPC: H03K5/24 ,  G11C5/14 ,  H01L27/00 ,  H01L27/108 ,  H01L27/146 ,  H01L49/02 ,  H01L21/78 ,  H01L23/498

Abstract: Provided is a semiconductor device that can directly compare two negative potentials. The semiconductor device includes a first to a third transistor and a load and is configured to compare a first negative potential and a second negative potential. The first negative potential and the second negative potential are input to a gate of the first transistor and a gate of the second transistor, respectively. Each drain of the first transistor and the second transistor is electrically connected to the load. The third transistor serves as a current source. The first transistor and the second transistor each include a backgate. A positive potential is input to the backgates.

公开(公告)号：US10446583B2

公开(公告)日：2019-10-15

申请号：US15911233

申请日：2018-03-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Yuto Yakubo ,  Shuhei Nagatsuka

IPC: H01L27/12 ,  H01L29/786 ,  H01L23/544 ,  H01L29/66

Abstract: To provide a semiconductor device that is not easily damaged by ESD in a manufacturing process thereof. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided to overlap with a dicing line. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided around the semiconductor device such as a transistor. The layer may be in a floating state or may be supplied with a specific potential.

公开(公告)号：US10192871B2

公开(公告)日：2019-01-29

申请号：US15698138

申请日：2017-09-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki ,  Kiyoshi Kato

IPC: H01L27/105 ,  H01L23/34 ,  H01L27/12 ,  H01L29/786 ,  H03K17/687 ,  G11C5/02 ,  G11C11/404 ,  G11C11/4097 ,  H01L27/108 ,  G11C11/40 ,  G11C11/4072 ,  G11C11/4094

Abstract: To provide a semiconductor device in which the on-state current is high and the operation speed is high. The semiconductor device includes a transistor, a first circuit, and a second circuit. The transistor includes a first gate and a second gate. The first gate and the second gate overlap with each other with a semiconductor layer positioned therebetween. The first circuit includes a temperature sensor. The temperature sensor obtains temperature information. The first circuit is configured to apply a voltage to the second gate depending on the temperature information. The first circuit preferably includes a comparator. The second circuit is configured to apply a negative voltage to the second gate and hold the negative voltage.

公开(公告)号：US10101606B2

公开(公告)日：2018-10-16

申请号：US15787920

申请日：2017-10-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Toshihiko Saito

IPC: G09G3/36 ,  G02F1/1333 ,  G02F1/1368 ,  H01L27/12 ,  G02F1/1343 ,  G06F3/041 ,  G06F3/044 ,  G02F1/1345

Abstract: A variable capacitor is formed from a pair of electrodes and a dielectric interposed between the electrodes over a substrate, and an external input is detected by changing capacitance of the variable capacitor by a physical or electrical force. Specifically, a variable capacitor and a sense amplifier are provided over the same substrate, and the sense amplifier reads the change of capacitance of the variable capacitor and transmits a signal in accordance with the input to a control circuit.

公开(公告)号：US10090333B2

公开(公告)日：2018-10-02

申请号：US14297692

申请日：2014-06-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato

IPC: H01L27/12 ,  G06F7/501 ,  G06F1/32 ,  H01L29/24 ,  H01L29/786

Abstract: In order to reduce power consumption, an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential set in accordance with the result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal. The arithmetic circuit includes an arithmetic portion performing the logic operation processing, a first field-effect transistor controlling whether a first potential, which is the potential corresponding to the result of the logic operation processing is set, and a second field-effect transistor controlling whether the potential of the output signal data is set at a second potential which is a reference potential.

公开(公告)号：US10056385B2

公开(公告)日：2018-08-21

申请号：US15427088

申请日：2017-02-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: G11C11/22 ,  H01L27/105 ,  G11C11/404 ,  G11C11/405 ,  G11C11/56 ,  H01L21/822 ,  H01L27/06 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/108 ,  H01L29/26 ,  G11C16/04 ,  G11C16/10 ,  H01L29/786 ,  G11C5/06 ,  G11C7/12 ,  H01L21/02 ,  H01L27/11521

CPC classification number: H01L27/1052 ,  G11C5/06 ,  G11C7/12 ,  G11C11/404 ,  G11C11/405 ,  G11C11/565 ,  G11C16/0408 ,  G11C16/10 ,  G11C2211/4016 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/263 ,  H01L29/7869

Abstract: Disclosed is a semiconductor device functioning as a multivalued memory device including: memory cells connected in series; a driver circuit selecting a memory cell and driving a second signal line and a word line; a driver circuit selecting any of writing potentials and outputting it to a first signal line; a reading circuit comparing a potential of a bit line and a reference potential; and a potential generating circuit generating the writing potential and the reference potential. One of the memory cells includes: a first transistor connected to the bit line and a source line; a second transistor connected to the first and second signal line; and a third transistor connected to the word line, bit line, and source line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor is connected to one of source and drain electrodes of the second transistor.

公开(公告)号：US09911756B2

公开(公告)日：2018-03-06

申请号：US15245310

申请日：2016-08-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Yuto Yakubo ,  Shuhei Nagatsuka

IPC: H01L27/12 ,  H01L23/544 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L27/1225 ,  H01L23/544 ,  H01L27/1207 ,  H01L27/1259 ,  H01L29/66969 ,  H01L29/7869 ,  H01L2223/54453

Abstract: To provide a semiconductor device that is not easily damaged by ESD in a manufacturing process thereof. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided to overlap with a dicing line. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided around the semiconductor device such as a transistor. The layer may be in a floating state or may be supplied with a specific potential.