公开(公告)号：US20140167116A1

公开(公告)日：2014-06-19

申请号：US14104993

申请日：2013-12-12

Applicant: STMicroelectronics S.A.

Inventor： Pascal Chevalier ,  Didier Celi ,  Jean-Pierre Blanc ,  Alain Chantre

IPC: H01L29/66 ,  H01L29/737

CPC classification number: H01L29/66242 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66325 ,  H01L29/737 ,  H01L29/7378

Abstract: The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation trenches, etching the silicon substrate in the first region to form a recess between the first and second isolation trenches,=; and forming a base of a heterojunction bipolar transistor by selective epitaxial growth of a film comprising SiGe in the recess.

Abstract translation: 本公开涉及一种方法，其包括在第一和第二隔离沟槽之间的第一区域中暴露硅衬底的表面，在第一区域中蚀刻硅衬底以在第一和第二隔离沟槽之间形成凹陷， 以及通过在凹部中选择性地外延生长包含SiGe的膜来形成异质结双极晶体管的基极。

公开(公告)号：US20140151561A1

公开(公告)日：2014-06-05

申请号：US13692691

申请日：2012-12-03

Applicant: STMICROELECTRONICS S.A.

Inventor： Hani Sherry ,  Andreia Cathelin

IPC: G01J5/34

CPC classification number: G01J5/34 ,  G05F3/26 ,  H01Q1/2283 ,  H01Q7/00 ,  H03K3/0315

Abstract: A pixel circuit including: a detection circuit having first and second transistors coupled in series between differential output nodes of an antenna, wherein the antenna is configured to be sensitive to terahertz radiation; a capacitor coupled to an intermediate node between the first and second transistors; and control circuitry coupled to control nodes of the first and second transistors, the control circuitry being configured for selectively applying to the control nodes one of: a gate biasing voltage for biasing the control nodes of the first and second transistors during a detection phase of the pixel circuit; and a reset voltage for resetting a voltage stored by the capacitor.

Abstract translation: 一种像素电路，包括：检测电路，其具有串联耦合在天线的差分输出节点之间的第一和第二晶体管，其中所述天线被配置为对太赫兹辐射敏感; 耦合到第一和第二晶体管之间的中间节点的电容器; 以及耦合到所述第一和第二晶体管的控制节点的控制电路，所述控制电路被配置为向所述控制节点选择性地施加以下之一：用于在所述第一和第二晶体管的检测阶段偏置所述第一和第二晶体管的控制节点的栅极偏置电压 像素电路; 以及用于复位由电容器存储的电压的复位电压。

公开(公告)号：US08722471B2

公开(公告)日：2014-05-13

申请号：US13748126

申请日：2013-01-23

Applicant: STMicroelectronics S.A. ,  Commissariat à l'Énergie Atomique et aux

Inventor： Perrine Batude ,  Yves Morand

IPC: H01L21/00

CPC classification number: H01L21/76843 ,  H01L21/76897 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823475

Abstract: A method for forming a via connecting a first upper level layer to a second lower level layer, both layers being surrounded with an insulating material, the method including the steps of: a) forming an opening to reach an edge of the first layer, the opening laterally continuing beyond said edge; b) forming a layer of a protection material on said edge only; c) deepening said opening by selectively etching the insulating material to reach the second lower level layer; and d) filling the opening with at least one conductive contact material.

Abstract translation: 一种用于形成连接第一上层与第二下层的通孔的方法，所述两层被绝缘材料包围，所述方法包括以下步骤：a）形成开口以到达第一层的边缘， 横向延伸超过所述边缘; b）仅在所述边缘上形成保护材料层; c）通过选择性地蚀刻绝缘材料到达第二较低层来加深所述开口; 以及d）用至少一个导电接触材料填充该开口。

公开(公告)号：US08704358B2

公开(公告)日：2014-04-22

申请号：US13688008

申请日：2012-11-28

Applicant: STMicroelectronics S.A.

Inventor： Pierre Bar ,  Sylvain Joblot ,  Nicolas Hotellier

IPC: H01L23/04

CPC classification number: H01L21/56 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/80 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/11009 ,  H01L2224/11334 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83203 ,  H01L2224/9202 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2224/80 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/05552

Abstract: A method for forming an integrated circuit including the steps of: a) forming openings in a front surface of a first semiconductor wafer, the depth of the openings being smaller than 10 μm, and filling them with a conductive material; b) forming doped areas of components in active areas of the front surface, forming interconnection levels on the front surface and leveling the surface supporting the interconnection levels; c) covering with an insulating layer a front surface of a second semiconductor wafer, and leveling the surface coated with an insulator; d) applying the front surface of the second wafer coated with insulator on the front surface of the first wafer supporting interconnection levels, to obtain a bonding between the two wafers; e) forming vias from the rear surface of the second wafer, to reach the interconnection levels of the first wafer; and f) thinning the first wafer to reach the openings filled with conductive material.

Abstract translation: 一种用于形成集成电路的方法，包括以下步骤：a）在第一半导体晶片的前表面形成开口，开口深度小于10μm，并用导电材料填充; b）在前表面的有源区域中形成组分的掺杂区域，在前表面上形成互连层，并平整支撑互连层的表面; c）用绝缘层覆盖第二半导体晶片的前表面，并平整涂有绝缘体的表面; d）将涂有绝缘体的第二晶片的前表面施加在第一晶片支撑互连电平的前表面上，以获得两个晶片之间的结合; e）从第二晶片的后表面形成通孔，以达到第一晶片的互连电平; 以及f）使第一晶片变薄以到达填充有导电材料的开口。

公开(公告)号：US20140061723A1

公开(公告)日：2014-03-06

申请号：US14017024

申请日：2013-09-03

Applicant: STMicroelectronics S.A.

Inventor： Vincent Quenette

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/7851

Abstract: A MOS transistor including a U-shaped channel-forming semiconductor region and source and drain regions having the same U shape located against the channel-forming region on either side thereof, the internal surface of the channel-forming semiconductor region being coated with a conductive gate, a gate insulator being interposed.

Abstract translation: 一种MOS晶体管，包括U形沟道形成半导体区域和具有相同U形的源极和漏极区域，其位于其任一侧上的沟道形成区域，沟道形成半导体区域的内表面涂覆有导电 栅极，插入栅极绝缘体。

公开(公告)号：US20130201766A1

公开(公告)日：2013-08-08

申请号：US13754427

申请日：2013-01-30

Applicant: STMICROELECTRONICS S.A.

Inventor： Anis Feki

IPC: G11C7/10 ,  G11C7/00

CPC classification number: G11C7/10 ,  G11C7/00 ,  G11C7/18 ,  G11C8/12 ,  G11C8/14 ,  G11C8/16

Abstract: A volatile memory includes volatile memory cells in which data write and read operations are performed. The memory cells are arranged in rows and in columns and are distributed in first separate groups of memory cells for each column. The memory includes, for each column, a write bit line dedicated to write operations and connected to all the memory cells of the column and read bit lines dedicated to read operations. Each read bit line is connected to all the memory cells of one of the first groups of memory cells. Each memory cell in the column is connected to a single one of the read bit lines.

Abstract translation: 易失性存储器包括执行数据写入和读取操作的易失性存储器单元。 存储单元以行和列排列并且分布在每列的第一分离的存储单元组中。 对于每列，存储器包括专用于写操作并连接到列的所有存储器单元的写位线，以及专用于读操作的读位线。 每个读位线连接到第一组存储器单元之一的所有存储单元。 列中的每个存储单元连接到单个读取位线。

公开(公告)号：US20040252554A1

公开(公告)日：2004-12-16

申请号：US10726263

申请日：2003-12-02

Applicant: STMicroelectronics S.A.

Inventor： Richard Fournel ,  Emmanuel Vincent ,  Sylvie Bruyere ,  Philippe Candelier ,  Francois Jacquet

IPC: G11C016/04

CPC classification number: G11C14/00 ,  G11C17/14

Abstract: An SRAM memory cell includes first and second inverters (14, 16) interconnected between first and second data nodes. Each inverter is formed from complementary MOS transistors (18, 20, 18null, 20null) connected in series between a DC voltage supply source and a grounding circuit (22). A circuit (28, 30) programs the MOS transistors by causing an irreversible degradation of a gate oxide layer of at least some of the transistors (18, 18null).

Abstract translation: SRAM存储单元包括在第一和第二数据节点之间互连的第一和第二反相器（14,16）。 每个反相器由串联连接在DC电压源和接地电路（22）之间的互补MOS晶体管（18,20,18'，20'）形成。 电路（28,30）通过使至少一些晶体管（18,18'）的栅极氧化层不可逆地退化来对MOS晶体管进行编程。

公开(公告)号：US20040251781A1

公开(公告)日：2004-12-16

申请号：US10814619

申请日：2004-03-31

Applicant: STMicroelectronics S.A.

Inventor： Guillaume Bouche ,  Pascal Ancey ,  Gregory Caruyer

IPC: H01L041/04

CPC classification number: B81B3/0078 ,  B81B2201/0271 ,  B81B2201/032 ,  B81B2203/0109 ,  H01G5/16 ,  H03H9/172 ,  H03H2009/02181

Abstract: A device comprising a resonator formed of a piezoelectric layer sandwiched between two metal electrodes, the resonator being laid on a suspended beam, the device comprising means for deforming said beam by the difference in thermal expansion coefficients.

Abstract translation: 一种包括由夹在两个金属电极之间的压电层形成的谐振器的装置，所述谐振器被放置在悬挂梁上，所述装置包括用于使所述光束变形所述热膨胀系数的差异的装置。

公开(公告)号：US20040246800A1

公开(公告)日：2004-12-09

申请号：US10860080

申请日：2004-06-03

Applicant: STMicroelectronics S.A.

Inventor： Franck Genevaux ,  Francois Jacquet

IPC: G11C007/00

CPC classification number: G11C7/12 ,  G11C7/065 ,  G11C2207/065

Abstract: A sense amplifier connected to first and second bit lines, comprising means for precharging said bit lines to a high voltage, means for connecting one or the other of the bit lines to a memory cell, said connection causing according to the state of the memory cell a maintaining of the bit line at the high voltage or a voltage reduction, first and second transistors respectively controlled by the first and second bit lines, and, in series with the first and second transistors, a controllable means for the current through the transistor controlled by the bit line connected to the memory cell to be greater than the current through the other transistor when the voltages of the two bit lines are at the high voltage.

Abstract translation: 连接到第一和第二位线的感测放大器包括用于将所述位线预充电到高电压的装置，用于将一个或另一个位线连接到存储器单元的装置，所述连接根据存储器单元的状态 分别由第一和第二位线控制的高电压或电压降低的位线的保持，以及与第一和第二晶体管串联的用于通过晶体管控制的电流的可控制装置 当两个位线的电压处于高电压时，连接到存储单元的位线大于通过另一个晶体管的电流。

公开(公告)号：US20040212410A1

公开(公告)日：2004-10-28

申请号：US10776931

申请日：2004-02-11

Applicant: STMicroelectronics S.A.

Inventor： Mostafa Ghazali ,  Pierre-Olivier Jouffre

IPC: H03L007/06

CPC classification number: H03L7/18 ,  H03L7/0891 ,  H03L7/0996

Abstract: A phase-locked loop comprising a comparator generating a control voltage depending on the phase-shift between a reference signal and a feedback signal, an oscillator controlled by the control voltage, generating several phase-shifted signals of same period, one of which forms the output signal of the phase-locked loop, a multiplexer capable of providing any of the phase-shifted signals to the input of a divider, the output of which forms the feedback signal, and a means controlling the multiplexer to successively provide fractions of the phase-shifted signals, so that the divider receives a signal having an average period equal to a real fraction of the period of the phase-shifted signals.

Abstract translation: 一种锁相环，包括比较器，其产生取决于参考信号和反馈信号之间的相移的控制电压，由控制电压控制的振荡器，产生相同周期的多个相移信号，其中之一形成 输出信号的多路复用器，能够将任何相移信号提供给分频器的输入，分频器的输出形成反馈信号，以及控制多路复用器的装置，以连续地提供相位的分数 转换信号，使得分频器接收具有等于相移信号的周期的实际分数的平均周期的信号。