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    Passing access line structure in a memory device
    253.
    发明授权
    Passing access line structure in a memory device 有权
    在存储设备中传递访问线路结构

    公开(公告)号：US09349737B2

    公开(公告)日：2016-05-24

    申请号：US14511371

    申请日：2014-10-10

    Applicant: Micron Technology, Inc.

    Inventor： Srinivas Pulugurtha ,  Sourabh Dhir ,  Rajesh N. Gupta ,  Sanh D. Tang ,  Si-Woo Lee ,  Haitao Liu

    IPC: H01L27/105 ,  H01L27/108 ,  G11C11/407

    CPC classification number: H01L27/10826 ,  G11C7/02 ,  G11C11/407 ,  G11C11/4097 ,  H01L27/10879

    Abstract: A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The continuous fins are etched into segmented fins to form exposed areas between the segmented fins. An insulator material is formed in the exposed areas wherein the insulator material in the exposed areas is formed higher than the insulator material around the fins. A metal is formed over the fins and the insulator material. The metal formed over the exposed areas is formed to a shallower depth than over the fins.

    Abstract translation: 用于存储器件制造的方法包括在衬底上形成多个连续的翅片。 在翅片周围形成绝缘体材料。 将连续的翅片蚀刻成分段的翅片以在分段翅片之间形成暴露的区域。 在暴露区域中形成绝缘体材料，其中暴露区域中的绝缘体材料形成为高于鳍片周围的绝缘体材料。 在翅片和绝缘体材料上形成金属。 形成在暴露区域上的金属形成为比鳍片上方浅的深度。

    Array Of Conductive Vias, Methods Of Forming A Memory Array, And Methods Of Forming Conductive Vias
    255.
    发明申请
    Array Of Conductive Vias, Methods Of Forming A Memory Array, And Methods Of Forming Conductive Vias 有权
    导电通孔阵列，形成存储器阵列的方法和形成导电通孔的方法

    公开(公告)号：US20150364414A1

    公开(公告)日：2015-12-17

    申请号：US14307121

    申请日：2014-06-17

    Applicant: Micron Technology, Inc.

    Inventor： Sanh D. Tang ,  Wolfgang Mueller ,  Brent Gilgen ,  Dylan R. Macmaster ,  Jim A. Jozwiak

    IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

    CPC classification number: H01L27/108 ,  H01L21/32133 ,  H01L21/76885 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10855 ,  H01L28/60 ,  H01L28/90

    Abstract: A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions individually comprise a dielectric top and dielectric sidewalls. A conductive line is formed elevationally over and angles relative to the line constructions. The conductive line comprises a longitudinally continuous portion and a plurality of conductive material extensions that individually extend elevationally inward between immediately adjacent of the line constructions. Etching is conducted elevationally through the longitudinally continuous portion and partially elevationally into the extensions at spaced locations along the conductive line to break-up the longitudinally continuous portion to form individual conductive vias extending elevationally between immediately adjacent of the line constructions. Methods of forming a memory array are also disclosed. Arrays of conductive vias independent of method of manufacture are also disclosed.

    Abstract translation: 形成导电通孔的方法包括在衬底上垂直地形成至少三个平行线结构。 线结构单独地包括电介质顶部和电介质侧壁。 导线在垂直方向上形成并相对于线结构形成。 导线包括纵向连续部分和多个导电材料延伸部，其在紧邻的线结构之间分别向内垂直延伸。 蚀刻通过纵向连续部分垂直地进行，并且沿着导电线在间隔开的位置部分地垂直地延伸到延伸部分中，以分解纵向连续部分，以形成在紧邻线结构之间垂直延伸的单个导电通孔。 还公开了形成存储器阵列的方法。 还公开了与制造方法无关的导电通孔的阵列。

    Arrays Of Vertically Stacked Tiers Of Non-Volatile Cross Point Memory Cells and Methods Of Reading A Data Value Stored By An Array Of Vertically Stacked Tiers Of Non-Volatile Cross Point Memory Cells
    258.
    发明申请
    Arrays Of Vertically Stacked Tiers Of Non-Volatile Cross Point Memory Cells and Methods Of Reading A Data Value Stored By An Array Of Vertically Stacked Tiers Of Non-Volatile Cross Point Memory Cells 有权
    非挥发性交叉点存储单元的垂直堆叠层阵列和读取由非易失性交叉点存储单元的垂直堆叠层阵列存储的数据值的方法

    公开(公告)号：US20140226392A1

    公开(公告)日：2014-08-14

    申请号：US14255283

    申请日：2014-04-17

    Applicant: Micron Technology, Inc.

    Inventor： Gurtej S. Sandhu ,  Sanh D. Tang

    IPC: G11C13/00

    CPC classification number: G11C13/0002 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C8/12 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/004 ,  G11C2213/71 ,  H01L27/0688 ,  H01L27/101

    Abstract: An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally oriented global bit lines having local vertical bit line extensions extend through multiple of the tiers. Individual of the memory cells comprise multi-resistive state material received between one of the horizontally oriented word lines and one of the local vertical bit line extensions where such cross, with such ones comprising opposing conductive electrodes of individual memory cells where such cross. A plurality of bit line select circuits individually electrically and physically connects to individual of the local vertical bit line extensions and are configured to supply a voltage potential to an individual of the global horizontal bit lines. Other embodiments and aspects are disclosed.

    Abstract translation: 垂直堆叠层的非易失性交叉点存储单元的阵列包括在存储单元的各个层内的多个水平取向的字线。 具有局部垂直位线延伸的多个水平定向的全局位线延伸穿过多个层。 存储单元的个体包括在水平定向的字线之一和本地垂直位线延伸之一中的一个之间接收的多电阻状态材料，其中这些交叉具有这样的交叉的单个存储器单元的相对的导电电极。 多个位线选择电路单独地电和物理地连接到本地垂直位线延伸的个体，并且被配置为向全局水平位线的个体提供电压电位。 公开了其它实施例和方面。

    METHODS OF FORMING SEMICONDUCTOR STRUCTURES INCLUDING BODIES OF SEMICONDUCTOR MATERIAL
    260.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR STRUCTURES INCLUDING BODIES OF SEMICONDUCTOR MATERIAL 有权
    形成半导体材料的半导体结构的方法

    公开(公告)号：US20140206175A1

    公开(公告)日：2014-07-24

    申请号：US14176780

    申请日：2014-02-10

    Applicant: Micron Technology, Inc.

    Inventor： Sanh D. Tang ,  David H. Wells ,  Tuman E. Allen

    IPC: H01L21/762

    CPC classification number: H01L29/792 ,  H01L21/02532 ,  H01L21/28282 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/84 ,  H01L27/1021 ,  H01L27/1027 ,  H01L27/10802 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/161 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

    Abstract: Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material. The bodies may be electrically coupled by one or more conductive structures, which may be used as an interconnect structure to electrically couple components of memory devices. By providing isolation between the bodies, the semiconductor structure provides the properties of a conventional SOI substrate (e.g., high speed, low power, increased device density and isolation) while substantially reducing fabrication acts and costs associated with such SOI substrates. Additionally, the semiconductor structures of the present disclosure provide reduced parasitic coupling and current leakage due to the isolation of the bodies by the intervening dielectric material.

    Abstract translation: 半导体结构包括与下面的衬底间隔开的半导体材料的主体。 物体可以通过介电材料，开放体积和导电材料中的至少一种与基底物理分离。 这些主体可以由一个或多个导电结构电耦合，其可以用作互连结构以电耦合存储器件的部件。 通过在主体之间提供隔离，半导体结构提供常规SOI衬底（例如，高速度，低功率，增加的器件密度和隔离）的性质，同时显着减少与这种SOI衬底相关联的制造动作和成本。 另外，本公开的半导体结构由于通过中间介电材料隔离物体而提供减小的寄生耦合和电流泄漏。

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