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    DEAD SURFACE INVALIDATION
    264.
    发明公开
    DEAD SURFACE INVALIDATION 审中-公开

    公开(公告)号：US20230206384A1

    公开(公告)日：2023-06-29

    申请号：US17563950

    申请日：2021-12-28

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Priyadarshi Sharma ,  Anshuman Mittal ,  Saurabh Sharma

    IPC: G06T1/60 ,  G06F12/0891 ,  G06T1/20

    CPC classification number: G06T1/60 ,  G06F12/0891 ,  G06T1/20 ,  G06F2212/455

    Abstract: Systems, apparatuses, and methods for performing dead surface invalidation are disclosed. An application sends draw call commands to a graphics processing unit (GPU) via a driver, with the draw call commands rendering to surfaces. After it is determined that a given surface will no longer be accessed by subsequent draw calls, the application sends a surface invalidation command for the given surface to a command processor of the GPU. After the command processor receives the surface invalidation command, the command processor waits for a shader engine to send a draw call completion message for a last draw call to access the given surface. Once the command processor receives the draw call completion message, the command processor sends a surface invalidation command to a cache to invalidate cache lines for the given surface to free up space in the cache for other data.

    FEATURE MANAGEMENT FOR MACHINE LEARNING SYSTEM
    266.
    发明公开
    FEATURE MANAGEMENT FOR MACHINE LEARNING SYSTEM 审中-公开

    公开(公告)号：US20230206113A1

    公开(公告)日：2023-06-29

    申请号：US17564126

    申请日：2021-12-28

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sergey Blagodurov

    IPC: G06N20/00

    CPC classification number: G06N20/00

    Abstract: A technique for processing images is disclosed. The technique includes tracking accesses, by a machine learning system, to individual features of a set of features, to generate an access count for each of the individual features; generating a rank for at least one of the individual features of the set of features based on the access count; and assigning the at least one of the individual features to a level of a memory hierarchy based on the rank.

    IOMMU COLLOCATED RESOURCE MANAGER
    267.
    发明公开
    IOMMU COLLOCATED RESOURCE MANAGER 审中-公开

    公开(公告)号：US20230205539A1

    公开(公告)日：2023-06-29

    申请号：US17565336

    申请日：2021-12-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sergey Blagodurov ,  Masab Ahmad

    IPC: G06F9/38 ,  G06F1/26 ,  G06N3/04

    CPC classification number: G06F9/3842 ,  G06F1/26 ,  G06N3/04

    Abstract: Devices, methods and systems for managing resources in a computing device. Information regarding resource usage is captured. A prediction is generated, based on the information, that resource usage by a processor will exceed a threshold during an upcoming time. An operating parameter of the processor is adjusted, based on the prediction. In some implementations, information regarding memory bandwidth is captured. A prediction is generated, based on the information, that a memory region stored in a first memory device will be addressed by a memory intensive instruction during an upcoming time period. Data stored in the memory region is moved to a second memory device, based on the prediction.

    PEAK ELECTRICAL CURRENT CONTROL OF SOC OR APU WITH MULTIPLE PROCESSOR CORES AND MULTIPLE GRAPHIC COMPUTE UNITS
    268.
    发明公开
    PEAK ELECTRICAL CURRENT CONTROL OF SOC OR APU WITH MULTIPLE PROCESSOR CORES AND MULTIPLE GRAPHIC COMPUTE UNITS 审中-公开

    公开(公告)号：US20230205304A1

    公开(公告)日：2023-06-29

    申请号：US17563788

    申请日：2021-12-28

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Xiuting C. Man ,  Xiaojie He ,  Michael Leonard Golden ,  Richard M. Born

    IPC: G06F1/3287 ,  G06F1/3206

    CPC classification number: G06F1/3287 ,  G06F1/3206

    Abstract: A system and method for efficient power management of an integrated circuit are described. In various implementations, a computing system includes an integrated circuit, multiple voltage regulators, and circuitry that detects when current drawn from a power rail from one of the multiple voltage regulators exceeds a limit. Upon detection, a single global alarm signal is asserted and conveyed to the integrate circuit. The integrated circuit includes at least a first group of functional blocks sharing a first power rail and a second group of functional blocks sharing a second power rail. When the global alarm signal is asserted, the functional blocks of the first group and the second group perform steps to immediately reduce power consumption. In order to maintain performance and satisfy a quality of service (QoS) parameter, a power management controller of the integrated circuit reassigns power limits shortly thereafter.

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