公开(公告)号：US09390925B1

公开(公告)日：2016-07-12

申请号：US14572975

申请日：2014-12-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/00 ,  H01L21/225 ,  H01L21/8234 ,  H01L29/161 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/18 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/161

Abstract: Constructing an SiGe fin by: (i) providing an intermediate sub-assembly including a silicon-containing base layer and a silicon-containing first fin structure extending in an upwards direction from the base layer; (ii) refining the sub-assembly by covering at least a portion of the top surface of the base layer and at least a portion of the first and second lateral surfaces of the first fin structure with a pre-thermal-oxidation layer that includes Silicon-Germanium (SiGe); and (iii) further refining the sub-assembly by thermally oxidizing the pre-thermal oxidation layer to migrate Ge content from the pre-thermal-oxidation layer into at least a portion of the base layer and at least a portion of first fin structure.

Abstract translation: 通过以下步骤构造SiGe翅片：（i）提供包括从基底层向上方延伸的含硅基底层和含硅的第一翅片结构的中间子组件; （ii）通过用包括硅的预热氧化层覆盖基层的顶表面的至少一部分和第一鳍结构的第一和第二侧表面的至少一部分来精炼子组件 锗（SiGe）; 和（iii）通过热氧化预热氧化层以使Ge含量从预热氧化层迁移到基层的至少一部分和第一翅片结构的至少一部分中，进一步细化子组件。

公开(公告)号：US09385231B2

公开(公告)日：2016-07-05

申请号：US14530796

申请日：2014-11-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/04 ,  H01L29/08 ,  H01L29/165 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/7841 ,  H01L29/78618 ,  H01L29/78654

Abstract: A FET structure including epitaxial source and drain regions includes large contact areas and exhibits both low resistivity and low parasitic gate to source/drain capacitance. The source and drain regions are laterally etched to provide recesses for accommodating low-k dielectric material without compromising the contact area between the source/drain regions and their associated contacts. A high-k dielectric layer is provided between the raised source/drain regions and a gate conductor as well as between the gate conductor and a substrate, such as an ETSOI or PDSOI substrate. The structure is usable in electronic devices such as MOSFET devices.

Abstract translation: 包括外延源极和漏极区域的FET结构包括大的接触区域，并且具有低电阻率和低的寄生栅极至源极/漏极电容。 源极和漏极区域被横向蚀刻以提供用于容纳低k电介质材料的凹部，而不损害源极/漏极区域及其相关联的接触之间的接触面积。 高K电介质层设置在凸起的源极/漏极区域和栅极导体之间​​以及栅极导体和诸如ETSOI或PDSOI衬底之类的衬底之间。 该结构可用于诸如MOSFET器件的电子器件中。

公开(公告)号：US09378948B2

公开(公告)日：2016-06-28

申请号：US14672157

申请日：2015-03-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/762 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/12 ,  H01L21/02 ,  H01L27/088 ,  H01L21/324 ,  H01L21/84 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167

CPC classification number: H01L21/02532 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76237 ,  H01L21/76283 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66795

Abstract: A finned structure is fabricated using a bulk silicon substrate having a carbon doped epitaxial silicon layer. A pFET region of the structure includes silicon germanium fins. Such fins are formed by annealing the structure to mix a germanium containing layer with an adjoining crystalline silicon layer. The structure further includes an nFET region including silicon fins formed from the crystalline silicon layer. The germanium containing layer in the nFET region is removed to create a space beneath the crystalline silicon layer in the nFET region. An insulating material is provided within the space. The pFET and nFET regions are electrically isolated by a shallow trench isolation region.

公开(公告)号：US09373637B2

公开(公告)日：2016-06-21

申请号：US14526767

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L27/12 ,  H01L27/06 ,  H01L29/06 ,  H01L29/36 ,  H01L29/417 ,  H01L49/02 ,  H01L21/84 ,  H01L27/13

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/13 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/36 ,  H01L29/41783

Abstract: An electrical device is provided that includes a substrate having an upper semiconductor layer, a buried dielectric layer and a base semiconductor layer. At least one isolation region is present in the substrate that defines a semiconductor device region and a resistor device region. The semiconductor device region includes a semiconductor device having a back gate structure that is present in the base semiconductor layer. Electrical contact to the back gate structure is provided by doped epitaxial semiconductor pillars that extend through the buried dielectric layer. An epitaxial semiconductor resistor is present in the resistor device region. Undoped epitaxial semiconductor pillars extending from the epitaxial semiconductor resistor to the base semiconductor layer provide a pathway for heat generated by the epitaxial semiconductor resistor to be dissipated to the base semiconductor layer. The undoped and doped epitaxial semiconductor pillars are composed of the same epitaxial semiconductor material.

公开(公告)号：US20160141368A1

公开(公告)日：2016-05-19

申请号：US14540051

申请日：2014-11-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic Schepis

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L29/1054 ,  H01L21/02123 ,  H01L21/76283 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/785

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming one or more tall strained silicon germanium (SiGe) fins on a semiconductor on insulator (SOI) substrate. The fins have a germanium (Ge) concentration which may differ from the Ge concentration within the top layer of the SOI substrate. The difference in Ge concentration between the fins and the top layer of the SOI substrate may range from approximately 10 atomic percent to approximately 40 atomic percent. This Ge concentration differential may be used to tailor a strain on the fins. The strain on the fins may be tailored to increase the critical thickness and allow for a greater height of the fins as compared to conventional strained fins of the same SiGe concentration formed from bulk material.

Abstract translation: 本发明一般涉及半导体器件，更具体地，涉及在绝缘体上半导体（SOI）衬底上形成一个或多个高应变硅锗（SiGe）鳍片的结构和方法。 散热片的锗（Ge）浓度可能与SOI衬底的顶层内的Ge浓度不同。 SOI衬底的翅片和顶层之间的Ge浓度的差可以在约10原子％至约40原子％的范围内。 该Ge浓度差可用于调节鳍片上的应变。 与散装材料形成的相同SiGe浓度的常规应变翅片相比，翅片上的应变可以被调整以增加临界厚度并允许翅片更大的高度。

公开(公告)号：US09343550B2

公开(公告)日：2016-05-17

申请号：US14666469

申请日：2015-03-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/762 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/7624 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/785

Abstract: A semiconductor device includes an insulator formed within a void to electrically isolate an active fin from an underlying substrate. The void is created by removing a sacrificial portion formed between the substrate and the active fin. The sacrificial portion may be doped to allow for a greater thickness relative to an un-doped portion of substantially similar composition. The doped sacrificial portion thickness may be between 10 nm and 250 nm. The thicker sacrificial portion allows for a thicker insulator so as to provide adequate electrical isolation between the active fin and the substrate. During formation of the void, the active fin may be supported by a gate. The semiconductor structure may also include a bulk region that has at least a maintained portion of the sacrificial portion material.

Abstract translation: 半导体器件包括形成在空隙内的绝缘体，以将活性鳍与下面的衬底电隔离。 通过去除形成在衬底和活性鳍片之间的牺牲部分来产生空隙。 牺牲部分可以被掺杂以允许相对于基本相似组成的未掺杂部分具有更大的厚度。 掺杂的牺牲部分厚度可以在10nm和250nm之间。 较厚的牺牲部分允许较厚的绝缘体，以便在活性鳍片和衬底之间提供足够的电绝缘。 在形成空隙期间，活性翅片可以由浇口支撑。 半导体结构还可以包括具有牺牲部分材料的至少保持部分的主体区域。

公开(公告)号：US09337050B1

公开(公告)日：2016-05-10

申请号：US14675045

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/8234

CPC classification number: H01L21/3086 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211

Abstract: One illustrative method disclosed herein includes, among other things, forming an inverted, generally T-shaped mandrel feature having a base mandrel structure and a substantially vertically oriented fin mandrel structure, the base mandrel structure having a lateral width that is greater than a lateral width of the fin mandrel structure, forming a sidewall spacer adjacent the sidewalls of the base mandrel structure and the fin mandrel structure, performing at least one etching process to remove portions of the inverted, generally T-shaped mandrel feature not covered by a sidewall spacer, wherein, after the etching process is completed, the sidewall spacers and remaining portions of the mandrel feature, collectively, define a fin pattern, and performing at least one additional process operation to form a plurality of fins in the substrate that correspond to the fin pattern.

Abstract translation: 本文公开的一种说明性方法包括形成具有基本心轴结构和基本垂直取向的翅片心轴结构的倒置的大体T形心轴特征，所述基部心轴结构具有大于横向宽度的横向宽度 形成翅片心轴结构的侧壁间隔件，邻近基部心轴结构和翅片心轴结构的侧壁形成侧壁间隔件，执行至少一个蚀刻工艺以去除未被侧壁间隔件覆盖的反向大体T形心轴特征的部分， 其中，在蚀刻工艺完成之后，所述侧壁间隔件和所述心轴特征的剩余部分共同地限定翅片图案，并执行至少一个附加工艺操作以在所述基板中形成对应于所述翅片图案的多个翅片 。

公开(公告)号：US20160126352A1

公开(公告)日：2016-05-05

申请号：US14994549

申请日：2016-01-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L21/84 ,  H01L29/08 ,  H01L27/12 ,  H01L29/04 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/7848 ,  H01L21/76283 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847

Abstract: A substrate including a handle substrate, a lower insulator layer, a buried semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. Semiconductor fins can be formed by patterning a portion of the buried semiconductor layer after removal of the upper insulator layer and the top semiconductor layer in a fin region, while a planar device region is protected by an etch mask. A disposable fill material portion is formed in the fin region, and a shallow trench isolation structure can be formed in the planar device region. The disposable fill material portion is removed, and gate stacks for a planar field effect transistor and a fin field effect transistor can be simultaneously formed. Alternately, disposable gate structures and a planarization dielectric layer can be formed, and replacement gate stacks can be subsequently formed.

Abstract translation: 提供了包括手柄基板，下绝缘体层，埋入半导体层，上绝缘体层和顶部半导体层的基板。 半导体鳍片可以通过在去除鳍片区域中的上绝缘体层和顶部半导体层之后图案化掩埋半导体层的一部分而形成，而平面器件区域被蚀刻掩模保护。 在翅片区域形成一次性填充材料部分，并且可以在平面装置区域中形成浅沟槽隔离结构。 去除一次性填充材料部分，并且可以同时形成用于平面场效应晶体管和鳍式场效应晶体管的栅极叠层。 或者，可以形成一次性栅极结构和平坦化介电层，并且随后可以形成替换栅极堆叠。

公开(公告)号：US09324870B2

公开(公告)日：2016-04-26

申请号：US14020923

申请日：2013-09-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L29/417 ,  H01L27/12

CPC classification number: H01L21/845 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L27/1211 ,  H01L29/32 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7856

Abstract: Merged and unmerged raised active regions on semiconductor fins can be simultaneously formed on a same substrate by control of growth rates of a deposited semiconductor material on surfaces of the semiconductor fins. In one embodiment, a growth-rate-retarding dopant can be implanted by angled ion implantation onto sidewall surfaces of first semiconductor fins on which retardation of growth rates is desired, while second semiconductor fins are masked by a masking layer. In another embodiment, a growth-rate-enhancing dopant can be implanted by ion implantation onto sidewall surfaces of second semiconductor fins, while first semiconductor fins are masked by a masking layer. The differential growth rates of the deposited semiconductor material can cause raised active regions on the first semiconductor fins to remain unmerged, and raised active regions on the second semiconductor fins to become merged.

Abstract translation: 通过控制半导体鳍片的表面上沉积的半导体材料的生长速率，可以在同一衬底上同时形成半导体鳍片上的合并和未熔合的凸起的有源区域。 在一个实施例中，生长速率缓冲掺杂剂可以通过成角度的离子注入注入第一半导体鳍片的侧壁表面上，在第二半导体鳍片被掩模层掩蔽的同时，其中需要延长生长速率。 在另一个实施例中，通过离子注入可以将生长速率增强掺杂剂注入到第二半导体鳍片的侧壁表面上，而第一半导体鳍片被掩蔽层掩蔽。 沉积的半导体材料的不同的生长速率可以使得第一半导体散热片上的凸起的有源区域保持不熔化，并且使第二半导体鳍片上的有源区域升高以合并。

公开(公告)号：US09318580B2

公开(公告)日：2016-04-19

申请号：US14590327

申请日：2015-01-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02494 ,  H01L21/02587 ,  H01L29/7853

Abstract: A method for forming a U-shaped semiconductor device includes growing a U-shaped semiconductor material along sidewalls and bottoms of trenches, which are formed in a crystalline layer. The U-shaped semiconductor material is anchored, and the crystalline layer is removed. Backfilling is formed underneath the U-shaped semiconductor material with a dielectric material for support. A semiconductor device is formed with the U-shaped semiconductor material.

Abstract translation: 形成U型半导体器件的方法包括沿形成在晶体层中的沟槽的侧壁和底部生长U形半导体材料。 U型半导体材料被锚固，并且去除晶体层。 在具有用于支撑的电介质材料的U形半导体材料下形成回填。 半导体器件由U形半导体材料形成。