Patent search ap:("MonolithIC 3D Inc.") AND inv:"Brian Cronquist" Page 27

261.

发明公开
3D SEMICONDUCTOR DEVICE, STRUCTURE AND METHODS WITH CONNECTIVITY STRUCTURES 审中-公开

公开(公告)号：US20240120320A1

公开(公告)日：2024-04-11

申请号：US18389752

申请日：2023-12-19

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Jin-Woo Han , Brian Cronquist , Eli Lusky

IPC: H01L25/065 , H01L23/00 , H01L23/473 , H01L23/48 , H10B80/00

CPC classification number: H01L25/0657 , H01L23/473 , H01L23/481 , H01L24/08 , H10B80/00 , H01L2224/08146 , H01L2225/06544 , H01L2924/1421 , H01L2924/1431

Abstract: A 3D device, the device including: at least one first level including logic circuits; at least one second level bonded to the first level, where the at least one second level includes a plurality of transistors; connectivity structures, where the connectivity structures include a plurality of transmission lines, where the plurality of transmission lines are designed to conduct radio frequencies (“RF”) signals, and where the bonded includes oxide to oxide bond regions and metal to metal bond regions; and a plurality of vias disposed through the at least one second level, where at least a majority of the plurality of vias have a diameter of less than 5 micrometers.

262.

发明授权
3D memory devices and structures with metal layers 有权

公开(公告)号：US11930648B1

公开(公告)日：2024-03-12

申请号：US18388840

申请日：2023-11-12

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Jin-Woo Han , Brian Cronquist

IPC: H10B80/00 , H01L23/00 , H01L25/00 , H01L25/065 , H01L25/18

CPC classification number: H10B80/00 , H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/1436 , H01L2924/14511

Abstract: A semiconductor device including: a first level including first memory arrays, a plurality of first transistors, and a plurality of first metal layers; a second level disposed on top of the first level, where the second level includes second memory arrays; a third level disposed on top of the second level, where the third level includes a plurality of third transistors and a plurality of third metal layers, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes, where the second filled holes are aligned to the first filled holes with a more than 1 nm but less than 40 nm alignment error, and where the third level includes decoder circuits.

263.

发明授权
3D semiconductor device and structure with metal layers 有权

公开(公告)号：US11916045B2

公开(公告)日：2024-02-27

申请号：US18236325

申请日：2023-08-21

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Brian Cronquist

IPC: H01L27/06 , H01L25/065 , H01L21/768 , H01L23/48 , H01L23/485 , H01L23/522 , H01L29/66 , H01L21/74 , H01L25/00 , H01L23/00 , H01L27/088 , H01L27/092 , H01L29/423 , H01L29/78

CPC classification number: H01L25/0657 , H01L21/743 , H01L21/76898 , H01L23/481 , H01L23/485 , H01L23/522 , H01L24/25 , H01L25/50 , H01L27/0688 , H01L27/088 , H01L29/66621 , H01L27/092 , H01L29/4236 , H01L29/78 , H01L2224/24146 , H01L2225/06544 , H01L2225/06589 , H01L2924/0002 , H01L2924/01104 , H01L2924/12032 , H01L2924/12042 , H01L2924/13091 , H01L2924/2064 , H01L2924/351

Abstract: A semiconductor device, the device including: a first substrate; a first metal layer disposed over the first substrate; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors each include single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 200 nm alignment error; and a via disposed through the first level, where the via has a diameter of less than 450 nm, where the fourth metal layer provides a global power distribution, and where the device includes at least one power supply circuit.

264.

发明公开
3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH BONDING 审中-公开

公开(公告)号：US20240055291A1

公开(公告)日：2024-02-15

申请号：US18382468

申请日：2023-10-20

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Brian Cronquist , Deepak C. Sekar

IPC: H01L21/683 , H01L21/74 , H01L21/762 , H01L21/768 , H01L21/822 , H01L21/8238 , H01L21/84 , H01L23/48 , H01L23/525 , H01L27/02 , H01L27/06 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/118 , H01L27/12 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/788 , H01L29/792 , G11C8/16 , H10B10/00 , H10B12/00 , H10B20/00 , H10B41/20 , H10B41/40 , H10B41/41 , H10B43/20 , H10B43/40

CPC classification number: H01L21/6835 , H01L21/743 , H01L21/76254 , H01L21/76898 , H01L21/8221 , H01L21/823828 , H01L21/84 , H01L23/481 , H01L23/5252 , H01L27/0207 , H01L27/0688 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/11807 , H01L27/11898 , H01L27/1203 , H01L29/4236 , H01L29/66272 , H01L29/66621 , H01L29/66825 , H01L29/66833 , H01L29/66901 , H01L29/78 , H01L29/7841 , H01L29/7843 , H01L29/7881 , H01L29/792 , G11C8/16 , H10B10/00 , H10B10/125 , H10B12/09 , H10B12/20 , H10B12/50 , H10B12/053 , H10B20/00 , H10B41/20 , H10B41/40 , H10B41/41 , H10B43/20 , H10B43/40 , H01L2924/13062 , H01L23/3677

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of DRAM memory cells, where each of the plurality of DRAM memory cells includes at least one of the second transistors, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.

265.

发明授权
3D semiconductor device and structure with memory 有权

公开(公告)号：US11901210B2

公开(公告)日：2024-02-13

申请号：US17880653

申请日：2022-08-04

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Brian Cronquist , Deepak C. Sekar

IPC: H01L21/683 , H01L21/74 , H01L21/762 , H01L21/768 , H01L21/822 , H01L21/8238 , H01L21/84 , H01L23/48 , H01L23/525 , H01L27/02 , H01L27/06 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/118 , H01L27/12 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/788 , H01L29/792 , G11C8/16 , H10B10/00 , H10B12/00 , H10B20/00 , H10B41/20 , H10B41/40 , H10B41/41 , H10B43/20 , H10B43/40 , H01L23/367 , H01L25/065 , H01L25/00 , H01L23/00 , H10B20/20

CPC classification number: H01L21/6835 , G11C8/16 , H01L21/743 , H01L21/76254 , H01L21/76898 , H01L21/8221 , H01L21/823828 , H01L21/84 , H01L23/481 , H01L23/5252 , H01L27/0207 , H01L27/0688 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/11807 , H01L27/11898 , H01L27/1203 , H01L29/4236 , H01L29/66272 , H01L29/66621 , H01L29/66825 , H01L29/66833 , H01L29/66901 , H01L29/78 , H01L29/7841 , H01L29/7843 , H01L29/7881 , H01L29/792 , H10B10/00 , H10B10/125 , H10B12/053 , H10B12/09 , H10B12/20 , H10B12/50 , H10B20/00 , H10B41/20 , H10B41/40 , H10B41/41 , H10B43/20 , H10B43/40 , H01L23/3677 , H01L24/13 , H01L24/16 , H01L24/45 , H01L24/48 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L27/1214 , H01L27/1266 , H01L2221/68368 , H01L2223/5442 , H01L2223/54426 , H01L2224/131 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/16235 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/81005 , H01L2224/83894 , H01L2225/06513 , H01L2225/06541 , H01L2924/00011 , H01L2924/01002 , H01L2924/01004 , H01L2924/01013 , H01L2924/01018 , H01L2924/01019 , H01L2924/01029 , H01L2924/01046 , H01L2924/01066 , H01L2924/01068 , H01L2924/01077 , H01L2924/01078 , H01L2924/01322 , H01L2924/10253 , H01L2924/10329 , H01L2924/12032 , H01L2924/12033 , H01L2924/12036 , H01L2924/12042 , H01L2924/1301 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/1579 , H01L2924/15311 , H01L2924/16152 , H01L2924/181 , H01L2924/19041 , H01L2924/3011 , H01L2924/3025 , H01L2924/30105 , H10B12/05 , H10B20/20

Abstract: A 3D semiconductor device including: a first level including a plurality of first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the plurality of first single-crystal transistors; a first metal layer disposed atop the plurality of first single-crystal transistors; a second metal layer disposed atop the first metal layer; a second level disposed atop the second metal layer, the second level including a plurality of second transistors; a third level including a plurality of third transistors, where the third level is disposed above the second level; a third metal layer disposed above the third level; and a fourth metal layer disposed above the third metal layer, where the plurality of second transistors are aligned to the plurality of first single crystal transistors with less than 140 nm alignment error, the second level includes first memory cells, the third level includes second memory cells.

266.

发明公开
MULTILEVEL SEMICONDUCTOR DEVICE AND STRUCTURE WITH IMAGE SENSORS AND WAFER BONDING 审中-公开

公开(公告)号：US20240047484A1

公开(公告)日：2024-02-08

申请号：US18382463

申请日：2023-10-20

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Deepak C. Sekar , Brian Cronquist

IPC: H01L27/146 , H04N25/78 , H04N25/77

CPC classification number: H01L27/14616 , H01L27/14636 , H04N25/78 , H04N25/77

Abstract: An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level with an oxide to oxide bond; a plurality of pixel control circuits; a plurality of memory circuits; and a third level disposed underneath the first level, where the third level includes a plurality of third transistors.

267.

发明公开
3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS 审中-公开

公开(公告)号：US20230395572A1

公开(公告)日：2023-12-07

申请号：US18236325

申请日：2023-08-21

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Brian Cronquist

IPC: H01L25/065 , H01L21/768 , H01L23/48 , H01L23/485 , H01L23/522 , H01L27/06 , H01L29/66 , H01L21/74 , H01L25/00 , H01L23/00 , H01L27/088

CPC classification number: H01L25/0657 , H01L21/76898 , H01L23/481 , H01L23/485 , H01L23/522 , H01L27/0688 , H01L29/66621 , H01L21/743 , H01L25/50 , H01L24/25 , H01L27/088 , H01L2924/12032 , H01L2924/13091 , H01L2924/351 , H01L2924/0002 , H01L27/092

Abstract: A semiconductor device, the device including: a first substrate; a first metal layer disposed over the first substrate; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors each include single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 200 nm alignment error; and a via disposed through the first level, where the via has a diameter of less than 450 nm, where the fourth metal layer provides a global power distribution, and where the device includes at least one power supply circuit.

268.

发明公开
3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH BONDING 审中-公开

公开(公告)号：US20230386886A1

公开(公告)日：2023-11-30

申请号：US18228675

申请日：2023-08-01

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Brian Cronquist , Deepak C. Sekar

IPC: H01L21/683 , H01L21/74 , H01L21/762 , H01L21/768 , H01L21/822 , H01L21/8238 , H01L21/84 , H01L23/48 , H01L23/525 , H01L27/02 , H01L27/06 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/118 , H01L27/12 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/788 , H01L29/792 , G11C8/16 , H10B10/00 , H10B12/00 , H10B20/00 , H10B41/20 , H10B41/40 , H10B41/41 , H10B43/20 , H10B43/40

CPC classification number: H01L21/6835 , H01L21/743 , H01L21/76254 , H01L21/76898 , H01L21/8221 , H01L21/823828 , H01L21/84 , H01L23/481 , H01L23/5252 , H01L27/0207 , H01L27/0688 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/11807 , H01L27/11898 , H01L27/1203 , H01L29/4236 , H01L29/66272 , H01L29/66621 , H01L29/66825 , H01L29/66833 , H01L29/66901 , H01L29/78 , H01L29/7841 , H01L29/7843 , H01L29/7881 , H01L29/792 , G11C8/16 , H10B10/00 , H10B10/125 , H10B12/09 , H10B12/20 , H10B12/50 , H10B12/053 , H10B20/00 , H10B41/20 , H10B41/40 , H10B41/41 , H10B43/20 , H10B43/40 , H01L2924/13062 , H01L23/3677

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the at least one of the second transistors transistor channel includes non-silicon atoms, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.