公开(公告)号：US5804909A

公开(公告)日：1998-09-08

申请号：US832841

申请日：1997-04-04

Applicant: Thomas Nilsson ,  John Song ,  Emmett Howard

Inventor： Thomas Nilsson ,  John Song ,  Emmett Howard

IPC: H01J3/02 ,  H01J19/24

CPC classification number: H01J3/022 ,  H01J2201/30423 ,  H01J2201/319

Abstract: An edge emission FED (100) includes a supporting substrate (110); a cathode (120) disposed on the supporting substrate (110); a ballast layer (130) disposed on the cathode (120); an emissive layer (140) disposed on the ballast layer (130) and defining an emissive edge (183); a field shaper layer (150) disposed on the emissive layer (140); a dielectric layer (160) disposed on the field shaper layer (150); a gate extraction electrode (170) disposed on the dielectric layer (160); an emission well (180) defined by the ballast layer (130), the emissive edge (183), the field shaper layer (150), the dielectric layer (160), and the gate extraction electrode (170); and an anode plate (188) opposing the gate extraction electrode (170).

Abstract translation: 边缘发射FED（100）包括支撑衬底（110）; 设置在所述支撑基板（110）上的阴极（120）; 设置在阴极（120）上的镇流器层（130）; 设置在所述镇流器层（130）上并限定发射边缘（183）的发射层（140）; 设置在所述发射层（140）上的场整形器层（150）; 设置在所述场整形器层（150）上的电介质层（160）; 设置在介电层（160）上的栅极引出电极（170）; 由镇流器层（130），发射边缘（183），场整形器层（150），电介质层（160）和栅极引出电极（170）限定的发射阱（180）。 以及与栅极引出电极（170）相对的阳极板（188）。

公开(公告)号：US5783910A

公开(公告)日：1998-07-21

申请号：US790205

申请日：1997-02-05

Applicant: Stephen L. Casper ,  Glen E. Hush ,  Thomas W. Voshell

Inventor： Stephen L. Casper ,  Glen E. Hush ,  Thomas W. Voshell

IPC: G09G3/00 ,  G09G3/20 ,  G09G3/22 ,  H01J31/12 ,  H05B33/12 ,  H05B41/36 ,  H05B41/392

CPC classification number: G09G3/006 ,  G09G3/22 ,  H01J31/127 ,  G09G2300/0809 ,  G09G2310/0248 ,  G09G2310/0259 ,  G09G2320/0606 ,  G09G2320/0626 ,  G09G2320/066 ,  G09G3/2011 ,  G09G3/2014 ,  H01J2201/319 ,  Y10S315/07

Abstract: This invention is directed to an improvement of a field emission display architecture in which low-voltage row and column address signals control a much higher pixel activation voltage. Instead of using a pair of series-coupled transistors the emitter node grounding path as in the original architecture (one of which is gated by a column signal d the other of which is gated by a row signal), only a single transistor is utilized in the emitter node grounding path thus eliminating an intermediate node between the two transistors that was responsible for unwanted emissions under certain operating conditions. In a preferred embodiment of the invention, a current regulating resistor is placed in the grounding path in series with the primary grounding transistor, with the resistor being directly coupled to ground. Additionally, for the preferred embodiment of the invention, the gate of the grounding transistor is coupled via a second field-effect transistor to either a row signal or a column signal. In the case where the gate of the first transistor is coupled to a row signal, the gate of the second transistor is coupled to a column signal. Likewise, where the gate of the first transistor is coupled to a column signal, the gate of the second transistor is coupled to a row signal. Numerous other equivalent circuits are possible, and several examples of such equivalent circuits are depicted in this disclosure.

Abstract translation: 本发明涉及一种场致发射显示结构的改进，其中低电压行和列地址信号控制高得多的像素激活电压。 代替使用一对串联耦合晶体管，如在原始架构（其中之一由列信号门控，其中另一个由行信号门控）的发射极节点接地路径，仅使用单个晶体管 发射极节点接地路径因此消除了在某些操作条件下负责不需要的发射的两个晶体管之间的中间节点。 在本发明的优选实施例中，电流调节电阻器被放置在与主接地晶体管串联的接地路径中，电阻器直接耦合到地。 此外，对于本发明的优选实施例，接地晶体管的栅极经由第二场效应晶体管耦合到行信号或列信号。 在第一晶体管的栅极耦合到行信号的情况下，第二晶体管的栅极耦合到列信号。 类似地，在第一晶体管的栅极耦合到列信号的情况下，第二晶体管的栅极耦合到行信号。 许多其他等效电路是可能的，并且在本公开中描述了这些等效电路的几个示例。

公开(公告)号：US5731597A

公开(公告)日：1998-03-24

申请号：US718876

申请日：1996-09-24

Applicant: Jong Duk Lee ,  Cheon Kyu Lee ,  Dong Hwan Kim

Inventor： Jong Duk Lee ,  Cheon Kyu Lee ,  Dong Hwan Kim

IPC: H01J17/49 ,  H01J1/304 ,  H01L27/00 ,  H01L29/06 ,  H01L29/12

CPC classification number: H01L27/00 ,  H01J1/3042 ,  H01J2201/319

Abstract: The present invention provides field emitter arrays (FEAs) incorporated with metal oxide semiconductor field effect transistors (MOSFETs) and method for fabricating the same which realizes a simultaneous fabrication of two kinds of devices, namely, an FEA and MOSFETs, by using common processing steps among the processes of fabricating Si-FEAs or metal FEAs and MOSFETs, wherein the method comprises steps of forming field emission tips and active regions for MOSFETs by oxidizing selected portions of a silicon nitride layer, forming a gate insulating oxide layer for the FEA and field oxide layers for MOSFETs simultaneously by the LOGOS method and connecting gate electrodes (row line) and cathode electrodes (column line) of the FEA to MOSFETs.

Abstract translation: 本发明提供了结合有金属氧化物半导体场效应晶体管（MOSFET）的场发射极阵列（FEAs）及其制造方法，其通过使用通用的处理步骤实现两种器件即FEA和MOSFET的同时制造 在制造Si-FEAs或金属FEAs和MOSFET的过程中，其中该方法包括以下步骤：通过氧化氮化硅层的选定部分形成用于MOSFET的场致发射尖端和有源区，形成用于FEA的场绝缘氧化物层和场 通过LOGOS方法同时进行MOSFET的氧化物层，并将FEA的栅电极（行线）和阴极电极（列线）连接到MOSFET。

公开(公告)号：US5726530A

公开(公告)日：1998-03-10

申请号：US727265

申请日：1996-10-07

Applicant: Chao-chi Peng

Inventor： Chao-chi Peng

IPC: H01J9/02 ,  H01J1/62 ,  H01J1/02 ,  H01J1/16 ,  H01J63/04

CPC classification number: H01J9/025 ,  H01J1/304 ,  H01J31/127 ,  H01J2201/319 ,  H01J2329/0494

Abstract: The object of the present invention is to provide a cold cathode field emission display whose resolution is not limited by the provision of individual ballast resistors for each pixel or by the wiring system used to deliver voltage to the cold cathodes. This has been achieved by providing additional layers beneath the cold cathodes arrays so that said resistors and voltage delivery systems are located directly below the cold cathode arrays instead of alongside of them. Six different embodiments of the invention are described.

Abstract translation: 本发明的目的是提供一种冷阴极场致发射显示器，其分辨率不受每个像素提供单个镇流电阻器的限制，或者通过用于向冷阴极传送电压的布线系统来限制。 这已经通过在冷阴极阵列之下提供附加层来实现，使得所述电阻器和电压输送系统位于冷阴极阵列的正下方而不是它们旁边。 描述本发明的六个不同实施例。

公开(公告)号：US5710478A

公开(公告)日：1998-01-20

申请号：US698260

申请日：1996-08-14

Applicant: Seigo Kanemaru ,  Junji Itoh

Inventor： Seigo Kanemaru ,  Junji Itoh

IPC: H01J1/304 ,  H01J1/308 ,  H01J1/30 ,  H01J19/24

CPC classification number: H01J3/022 ,  H01J1/3042 ,  H01J1/308 ,  H01J2201/319

Abstract: A field emission device of simple structure enables stabilization and control of field emission current. A three-dimensional emitter formed on a base member incorporates therein a source layer on the side in contact with the base member, a drain layer on the side of the distal end including a tip and a channel region layer between the source layer and the drain layer. A gate is formed near the emitter. A strong electric field generated by applying a voltage to the gate causes cold electrons to be emitted from the emitter tip and the voltage applied to the gate also controls the conductivity of the channel region layer, whereby the field emission current emitted from the tip of the emitter is stabilized and controlled.

Abstract translation: 具有简单结构的场致发射器件可实现场发射电流的稳定和控制。 形成在基底构件上的三维发射体在其中包括与基底构件接触的一侧的源极层，在远端侧的漏极层包括尖端和在源极层和漏极之间的沟道区域层 层。 在发射极附近形成栅极。 通过向栅极施加电压产生的强电场使得发射极尖端发出冷电子，并且施加到栅极的电压也控制沟道区域层的导电性，从而从 发射极稳定并受到控制。

公开(公告)号：US5696028A

公开(公告)日：1997-12-09

申请号：US300616

申请日：1994-09-02

Applicant: J. Brett Rolfson ,  Kevin Tjaden

Inventor： J. Brett Rolfson ,  Kevin Tjaden

IPC: H01J9/02 ,  H01L21/3105 ,  H01J9/00 ,  H01J9/24 ,  H01L21/465

CPC classification number: H01L21/31053 ,  H01J9/025 ,  H01J2201/30426 ,  H01J2201/319 ,  H01J2209/0226

Abstract: A field emitter display having reduced surface leakage comprising at least one emitter tip surrounded by a dielectric region. The dielectric region is formed of a composite of insulative layers, at least one of which has fins extending toward the emitter tip. A conductive gate, for extracting electrons from the emitter tip, is disposed superjacent the dielectric region. The fins increase the length of the path that leaked electrical charge travels before impacting the gate.

Abstract translation: 具有减小的表面泄漏的场发射器显示器包括由电介质区域包围的至少一个发射极尖端。 电介质区域由绝缘层的复合体形成，其中至少一个具有朝向发射极尖端延伸的翅片。 用于从发射极尖端提取电子的导电栅极设置在电介质区域的上方。 在撞击门之前，翅片增加了泄漏电荷行进路径的长度。

公开(公告)号：US5672933A

公开(公告)日：1997-09-30

申请号：US550050

申请日：1995-10-30

Applicant: Arthur M. Wilson ,  Robert H. Taylor ,  Chi-Cheong Shen

Inventor： Arthur M. Wilson ,  Robert H. Taylor ,  Chi-Cheong Shen

IPC: H01J1/304 ,  H01J1/30

CPC classification number: H01J1/3042 ,  H01J2201/319

Abstract: An electron emitter plate (10, 10') for an FED image display has a gate conductive layer (22) spaced by a dielectric insulating layer (25) from a cathode conductive layer formed into a mesh (18). Arrays (12) of microtips (14) are located within mesh spacings (16) for field emission of electrons toward a phosphor layer (34) of an anode plate (11). Cathode layer (18) is patterned into column stripes (19) separated by gaps (17). Gate layer (22) is patterned into row cross-stripes (24) separated by gaps (23) which intersect with stripes (19) at matrix addressable pixel locations (30). Resistive layer (15) is patterned into stripes (40) separated by gaps (42) which interrupt column-to-column electrical communication through resistive layer (15). Unetched strips (43) are provided to bridge gap discontinuities for deposition of gate layer (22) at crossovers of rows (24) between columns (19). In one embodiment, gate layer (22) has a mesh pattern with apertured pads (46) commonly connected along resistive gap edges by marginal buses (50) formed on borders (49) of resistive layer (15) along gaps (42). Adjacent marginal buses (50) are connected by crossover buses (52) formed over bridging strips (43).

Abstract translation: 用于FED图像显示器的电子发射极板（10,10'）具有由形成为网状物（18）的阴极导电层与电介质绝缘层（25）隔开的栅极导电层（22）。 小尖头（14）的阵列（12）位于网格间隔（16）内，用于向阳极板（11）的荧光体层（34）发射电子。 阴极层（18）被图案化成由间隙（17）分开的列条纹（19）。 栅极层（22）被图案化成由在矩阵可寻址像素位置（30）处与条纹（19）相交的间隙（23）分开的行交叉条纹（24）。 电阻层（15）被图案化成由间隙（42）分开的条纹（40），间隙（42）通过电阻层（15）中断列对电连通。 提供未锯齿条（43）以桥接间隙不连续性，用于在柱（19）之间的行（24）的交叉处沉积栅极层（22）。 在一个实施例中，栅极层（22）具有网格图案，其中孔径焊盘（46）通过沿着间隙（42）形成在电阻层（15）的边界（49）上的边缘总线（50）沿着电阻性间隙边缘共同连接。 相邻边缘总线（50）通过形成在桥接条（43）上的交叉总线（52）连接。

公开(公告)号：US5656886A

公开(公告)日：1997-08-12

申请号：US580613

申请日：1995-12-29

Applicant: Michael J. Westphal ,  Behnam Moradi

Inventor： Michael J. Westphal ,  Behnam Moradi

IPC: H01J9/02 ,  H01J9/12 ,  H01J1/46 ,  H01J1/62 ,  H01J21/10 ,  H01J63/04

CPC classification number: H01J9/025 ,  H01J2201/319

Abstract: Cold cathode passive matrix FEDs are fabricated by depositing a resistive layer on a substrate, and coated with a protective layer in which at least one hole is formed. Cathode material is deposited on the protective layer making direct contact with the resistive layer through the hole to form bases for the emitter tips which are subsequently etched from the cathode layer. The protective layer allows overetching of the cathode material to prevent tip-to-tip electrical shorts without attacking the underlying resistive layer.

Abstract translation: 冷阴极无源矩阵FED通过在衬底上沉积电阻层并涂覆有形成至少一个孔的保护层来制造。 阴极材料沉积在保护层上，通过孔与电阻层直接接触，形成发射极尖端的基底，随后从阴极层进行蚀刻。 保护层允许阴极材料的过蚀刻以防止尖端到尖端的电短路而不侵害下面的电阻层。

公开(公告)号：US5650689A

公开(公告)日：1997-07-22

申请号：US598420

申请日：1996-02-08

Applicant: Shigeo Itoh ,  Teruo Watanabe ,  Kazuhiko Tsuburaya ,  Yoshihiko Hirata ,  Susumu Takada ,  Hiroshi Nakagawa

Inventor： Shigeo Itoh ,  Teruo Watanabe ,  Kazuhiko Tsuburaya ,  Yoshihiko Hirata ,  Susumu Takada ,  Hiroshi Nakagawa

IPC: H01J9/02 ,  H01J1/304 ,  H01J1/02 ,  H01J1/14 ,  H01J1/16 ,  H01J19/10

CPC classification number: H01J1/3042 ,  H01J2201/319

Abstract: A field emission element including an electrode structure made of a thin film exhibiting increased adhesive strength. A thin film of niobium nitride (NbN) is formed on a glass substrate by sputtering or the like. The NbN film exhibits increased adhesive strength to a degree sufficient to prevent etching for formation of the film into electrodes from causing peeling of the film.

Abstract translation: 一种场发射元件，包括由表现出增加的粘合强度的薄膜制成的电极结构。 通过溅射等在玻璃基板上形成氮化铌（NbN）的薄膜。 NbN膜的粘合强度提高到足以防止膜形成电极的蚀刻从而引起膜剥离的程度。

公开(公告)号：US5612712A

公开(公告)日：1997-03-18

申请号：US479270

申请日：1995-06-07

Applicant: Nalin Kumar ,  Chenggang Xie

Inventor： Nalin Kumar ,  Chenggang Xie

IPC: G09G3/22 ,  G09G3/30 ,  H01J1/304 ,  H01J9/02 ,  H01J29/04 ,  H01J29/08 ,  H01J29/28 ,  H01J31/12 ,  H01J61/067 ,  H01J63/06

CPC classification number: H01J1/304 ,  G09G3/22 ,  H01J1/3042 ,  H01J29/085 ,  H01J31/127 ,  H01J61/0677 ,  H01J63/06 ,  H01J9/027 ,  H01J2201/304 ,  H01J2201/30426 ,  H01J2201/30457 ,  H01J2201/319 ,  H01J2329/8625 ,  H01J2329/864

Abstract: A matrix-addressed diode flat panel display of field emission type is described, utilizing a diode (two terminal) pixel structure. The flat panel display comprises a cathode assembly having a plurality of cathodes, each cathode including a layer of cathode conductive material and a layer of a low effective work-function material deposited over the cathode conductive material and an anode assembly having a plurality of anodes, each anode including a layer of anode conductive material and a layer of cathodoluminescent material deposited over the anode conductive material, the anode assembly located proximate the cathode assembly to thereby receive charged particle emissions from the cathode assembly, the cathodoluminescent material emitting light in response to the charged particle emissions. The flat panel display further comprises means for selectively varying field emission between the plurality of corresponding light-emitting anodes and field-emission cathodes to thereby effect an addressable grey-scale operation of the flat panel display.

Abstract translation: 利用二极管（二端）像素结构描述场发射型矩阵寻址二极管平板显示器。 平板显示器包括具有多个阴极的阴极组件，每个阴极包括阴极导电材料层和沉积在阴极导电材料上的低有效功函数材料层和具有多个阳极的阳极组件， 每个阳极包括阳极导电材料层和沉积在阳极导电材料上的阴极发光材料层，阳极组件位于阴极组件附近，从而接收来自阴极组件的带电粒子发射，阴极发光材料响应于 带电粒子排放。 平板显示器还包括用于选择性地改变多个对应的发光阳极和场发射阴极之间的场发射的装置，从而实现平板显示器的可寻址的灰度级操作。