公开(公告)号：US10430200B2

公开(公告)日：2019-10-01

申请号：US15676453

申请日：2017-08-14

Applicant: Xilinx, Inc.

Inventor： Patrick Lysaght ,  Graham F. Schelle ,  Parimal Patel ,  Peter K. Ogden

IPC: G06F9/38 ,  G06F9/30

Abstract: An integrated circuit can include a slave processor configured to execute instructions. The slave processor can be implemented in programmable circuitry of the integrated circuit. The integrated circuit also can include a processor coupled to the slave processor. The processor can be hardwired and configured to control operation of the slave processor.

公开(公告)号：US20190288830A1

公开(公告)日：2019-09-19

申请号：US15920251

申请日：2018-03-13

Applicant: Xilinx, Inc.

Inventor： Yi Zhuang ,  Winson Lin ,  Jinyung Namkoong ,  Hsung Jai Im ,  Stanley Y. Chen

IPC: H04L7/033 ,  H04L7/00 ,  H03K19/0175 ,  G06F1/06

Abstract: A circuit for receiving a signal in an integrated circuit is described. The circuit comprises a sampler configured to receive an input data signal, wherein the sampler generates sampled data and a recovered clock; a clock and data recovery circuit configured to receive the sampled data and the recovered clock and to generate a phase interpolator code; and a phase interpolator configured to receive the phase interpolator code; wherein the phase interpolator generates multiple phase interpolator control signals during a clock cycle based upon the phase interpolator code generated for the clock cycle.

公开(公告)号：US10419203B1

公开(公告)日：2019-09-17

申请号：US15444002

申请日：2017-02-27

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini ,  Antonello Di Fresco

IPC: H04L7/033

Abstract: An example circuit includes: a transmitter configured to transmit a clock pattern based on a transmit clock; a receiver, coupled to the transmitter, configured to sample the clock pattern based on a receive clock to generate a bit pattern, where there is a non-zero frequency difference between the transmit clock and the receive clock; a phase interpolator (PI) configured to add a phase shift to a source clock to supply one of the transmit clock or the receive clock; and a test circuit configured to apply adjustments to the phase shift over a time period and determine a phase distribution of the PI based on changes in the bit pattern over the time period.

公开(公告)号：US20190280086A1

公开(公告)日：2019-09-12

申请号：US15917206

申请日：2018-03-09

Applicant: Xilinx, Inc.

Inventor： James Karp ,  Michael J. Hart

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: FinFET, P-N junctions and methods for forming the same are described herein. In one example, a FinFET transistor is described that includes a fin having a channel region wrapped by a gate, the channel region connecting a source and a drain. A first isolation layer is disposed on a first side of the in and a second isolation layer is disposed on a second side of the fin, where the second side is opposite of the first side. The second oxide isolation layer has a thickness greater than a thickness of the first isolation layer.

公开(公告)号：US10404445B1

公开(公告)日：2019-09-03

申请号：US16026967

申请日：2018-07-03

Applicant: Xilinx, Inc.

Inventor： Hongtao Zhang ,  Jinyung NamKoong ,  Winson Lin ,  Yohan Frans ,  Geoffrey Zhang

IPC: H03D3/24 ,  H04L7/00 ,  H04L7/033 ,  H03L7/081

Abstract: A receiver circuit for receiving data is described. The receiver circuit comprises a phase detector configured to receive an input data signal; a frequency path circuit configured to receive an output of the phase detector; and a false lock detection circuit configured to receive the output of the phase detector and an output of the frequency path circuit; wherein the false lock detection circuit detects a false lock of the receiver circuit to the input data signal based upon an output of the phase detector and provides a frequency offset to the frequency path circuit. A method of receiving data is also described.

公开(公告)号：US10404265B1

公开(公告)日：2019-09-03

申请号：US16117650

申请日：2018-08-30

Applicant: Xilinx, Inc.

Inventor： Brendan Farley ,  Bruno Miguel Vaz ,  Darragh Walsh

IPC: H03M1/80 ,  H03F3/30

Abstract: An example apparatus includes a first transistor coupled between a supply node and a first node, a current mirror having a first side and a second side, and a second transistor coupled between the first node and the first side of the current mirror. The input buffer further includes a third transistor coupled between the first node and the second side of the current mirror, and a first capacitor coupled between a source and a drain of the second transistor.

公开(公告)号：US10387600B2

公开(公告)日：2019-08-20

申请号：US15266827

申请日：2016-09-15

Applicant: Xilinx, Inc.

Inventor： Chaithanya Dudha ,  Krishna Garlapati

IPC: G06F17/50 ,  G06F1/32

Abstract: Reducing dynamic power consumption for a circuit can include analyzing, using a processor, a netlist specifying the circuit to determine a block of combinatorial circuitry in a first signal path with at least a threshold amount of switching activity and detecting, using the processor, a second signal path coupled to the block of combinatorial circuitry by a sequential circuit element. The second signal path has a delay that meets a target signal path requirement. Using the processor, the netlist can be modified by subdividing the block of combinatorial circuitry into at least a first portion and a second portion and moving one of the portions from the first signal path to the second signal path, wherein the moving separates the first portion from the second portion by the sequential circuit element.

公开(公告)号：US10387594B1

公开(公告)日：2019-08-20

申请号：US15707897

申请日：2017-09-18

Applicant: Xilinx, Inc.

Inventor： Chinmaya Dash

IPC: G06F17/50 ,  H03K19/01 ,  H03K19/17 ,  H03K19/0175 ,  H03K19/177

Abstract: An integrated circuit having programmable logic fabric, as well as system and method for computer aided design using such integrated circuit, are disclosed. This integrated circuit includes: a configurable bypassable flip-flop circuit configured to transfer information from programmable internal routing to an input bus of a programmable logic circuit; a loopback branch connected to the input bus to bypass the programmable logic circuit; and a multiplexer having a first input port connected to the loopback branch, a second input port connected to an output bus of the programmable logic circuit, and an output port connected to routing switches of the programmable internal routing. The multiplexer is configured to electrically couple either the first input port or the second input port to the output port.

公开(公告)号：US20190243781A1

公开(公告)日：2019-08-08

申请号：US15892266

申请日：2018-02-08

Applicant: Xilinx, Inc.

Inventor： Chandrasekhar S Thyamagondlu ,  Darren Jue ,  Tao Yu ,  John West ,  Hanh Hoang ,  Ravi Sunkavalli

IPC: G06F12/1081

CPC classification number: G06F12/1081 ,  G06F2212/621 ,  G06F2213/28

Abstract: Examples herein describe techniques for providing a customizable direct memory access (DMA) interface which can permit user logic to change or control how DMA read and writes are performed. In one example, a DMA engine may be hardened (e.g., include circuitry formed from a semiconductor material) which prevents the DMA engine from being reconfigured like programmable logic. Instead of changing the DMA engine, the user logic can change or customize the DMA interface between the user logic and the DMA engine. In this way, the manner in which the DMA engine performs DMA write and reads can be changed by the user logic. In one example, the DMA engine includes a bypass mode of operation where descriptors associated with DMA queues are passed through the DMA engine and to the user logic.

公开(公告)号：US10366201B1

公开(公告)日：2019-07-30

申请号：US15495760

申请日：2017-04-24

Applicant: Xilinx, Inc.

Inventor： Aaron Ng ,  Sridhar Krishnamurthy ,  Grigor S. Gasparyan

IPC: G06F9/455 ,  G06F17/50

Abstract: Closing timing for a circuit design can include displaying, using a display device, a first region having a plurality of controls corresponding to a plurality of data sets generated at different times during a phase of a design flow for a circuit design, wherein each control selects a data set associated with the control, and displaying, using the display device, a second region configured to display a list of critical paths for data sets selected from the first region using one of the plurality of controls. Closing timing further can include displaying, using the display device, a third region configured to display a representation of a target integrated circuit including layouts for the critical paths of the list for implementations of the circuit design specified by the selected data sets.