公开(公告)号：US09257536B2

公开(公告)日：2016-02-09

申请号：US13867247

申请日：2013-04-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan

IPC: H01L29/66

CPC classification number: H01L29/66795

Abstract: FinFET structures and methods of formation are disclosed. Fins are formed on a bulk substrate. A crystalline insulator layer is formed on the bulk substrate with the fins sticking out of the epitaxial oxide layer. A gate is formed around the fins protruding from the crystalline insulator layer. An epitaxially grown semiconductor region is formed in the source drain region by merging the fins on the crystalline insulator layer to form a fin merging region.

Abstract translation: 公开了FinFET结构和形成方法。 翅片形成在块状基底上。 在散装衬底上形成结晶绝缘体层，翅片从外延氧化物层伸出。 在从结晶绝缘体层突出的翅片周围形成栅极。 通过将结晶绝缘体层上的翅片合并形成翅片合并区域，在源漏区域中形成外延生长的半导体区域。

公开(公告)号：US20160035863A1

公开(公告)日：2016-02-04

申请号：US14883049

申请日：2015-10-14

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Ajey P. Jacob ,  Witold P. Maszara ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/66 ,  H01L29/165 ,  H01L21/02 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7849 ,  H01L29/785

Abstract: An illustrative method includes forming a FinFET device above structure comprising a semiconductor substrate, a first epi semiconductor material and a second epi semiconductor material that includes forming an initial fin structure that comprises portions of the semiconductor substrate, the first epi material and the second epi material, recessing a layer of insulating material such that a portion, but not all, of the second epi material portion of the initial fin structure is exposed so as to define a final fin structure, forming a gate structure above and around the final fin structure, removing the first epi material of the initial fin structure and thereby define an under-fin cavity under the final fin structure and substantially filling the under-fin cavity with a stressed material.

Abstract translation: 一种说明性的方法包括在包括半导体衬底，第一外延半导体材料和第二外延半导体材料的结构之上形成FinFET器件，其包括形成包括半导体衬底，第一外延材料和第二外延材料的部分的初始鳍结构 使一层绝缘材料凹陷，使得初始翅片结构的第二外延材料部分的一部分（但不是全部）暴露以便限定最终的翅片结构，在最后的翅片结构的上方和周围形成栅极结构， 去除初始翅片结构的第一外延材料，从而在最终翅片结构下限定底鳍腔，并用应力材料基本上填充底鳍腔。

公开(公告)号：US09246003B2

公开(公告)日：2016-01-26

申请号：US14083517

申请日：2013-11-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Eric C. Harley ,  Yue Ke ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L29/772 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7842 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor structure may include a semiconductor fin, a gate over the semiconductor fin, a spacer on a sidewall of the gate, an angled recess region in an end of the semiconductor fin beneath the spacer, and a first semiconductor region filling the angled recess. The angled recess may be v-shaped or sigma shaped. The structure may further include a second semiconductor region in contact with the first semiconductor region and the substrate. The structure may be formed by forming a gate above a portion of the semiconductor fin on a substrate, forming a spacer on a sidewall of the gate; removing a portion of the semiconductor fin not covered by the spacer or the gate to expose a sidewall of the fin, etching the sidewall of the fin to form an angled recess region beneath the spacer, and filling the angled recess region with a first epitaxial semiconductor region.

Abstract translation: 半导体结构可以包括半导体鳍片，半导体鳍片上的栅极，栅极的侧壁上的间隔物，在间隔物下方的半导体鳍片的端部中的成角度的凹陷区域以及填充成角度的凹部的第一半导体区域。 成角度的凹槽可以是v形或西格玛形。 该结构还可以包括与第一半导体区域和衬底接触的第二半导体区域。 该结构可以通过在衬底上形成半导体翅片的一部分上方的栅极形成，在栅极的侧壁上形成间隔物; 除去未被间隔物或栅极覆盖的半导体鳍片的一部分以暴露翅片的侧壁，蚀刻翅片的侧壁以在间隔物下方形成倾斜的凹陷区域，并用第一外延半导体填充成角度的凹陷区域 地区。

公开(公告)号：US09219139B2

公开(公告)日：2015-12-22

申请号：US14081320

申请日：2013-11-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/20

CPC classification number: H01L29/78 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/20 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device including at least two fin structures on a substrate surface and a functional gate structure present on the at least two fin structures. The functional gate structure includes at least one gate dielectric that is in direct contact with at least the sidewalls of the two fin structures, and at least one gate conductor on the at least one gate dielectric. The sidewall of the gate structure is substantially perpendicular to the upper surface of the substrate surface, wherein the plane defined by the sidewall of the gate structure and a plane defined by an upper surface of the substrate surface intersect at an angle of 90°+/−5°. An epitaxial semiconductor material is in direct contact with the at least two fin structures.

Abstract translation: 一种半导体器件，包括在衬底表面上的至少两个鳍结构和存在于所述至少两个鳍结构上的功能栅结构。 功能栅极结构包括至少一个与至少两个鳍结构的侧壁直接接触的栅极电介质，以及至少一个栅极电介质上的至少一个栅极导体。 栅极结构的侧壁基本上垂直于衬底表面的上表面，其中由栅极结构的侧壁限定的平面和由衬底表面的上表面限定的平面以90°±/ -5°。 外延半导体材料与至少两个翅片结构直接接触。

公开(公告)号：US09219078B2

公开(公告)日：2015-12-22

申请号：US13865795

申请日：2013-04-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc. ,  GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Qing Liu ,  Nicolas Loubet ,  Scott Luning

IPC: H01L27/12 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L21/84 ,  H01L29/10

CPC classification number: H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/4966

Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.

Abstract translation: 一种用于半导体制造的方法包括在包括至少一个硅锗（SiGe）沟道区的衬底上提供沟道区，所述衬底包括包括第一区和第二区的多个区域。 对于第一区域中的第一n型场效应晶体管（NFET）和第一p型场效应晶体管（PFET）以及第二区域中的第二NFET和第二PFET形成栅极结构， 第一PFET形成在SiGe沟道区上。 用于第一NFET的栅极结构包括具有第一功函数的栅极材料，并且用于第一PFET，第二NFET和第二PFET的栅极结构包括具有第二功函数的栅极材料，使得提供多阈值电压器件。

公开(公告)号：US09214397B2

公开(公告)日：2015-12-15

申请号：US13788689

申请日：2013-03-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bruce B. Doris ,  Kangguo Cheng ,  Steven J. Holmes ,  Ali Khakifirooz ,  Pranita Kerber ,  Shom Ponoth ,  Raghavasimhan Sreenivasan ,  Stefan Schmitz

IPC: H01L21/8238

CPC classification number: H01L21/823835 ,  H01L21/823842

Abstract: A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.

Abstract translation: 一种用于形成电气装置的方法，包括在半导体衬底上形成高k栅介质层，该半导体衬底被图案化以将存在于第一导电器件区域上的高k栅介质层的第一部分与第二部分分离 存在于第二导电装置区域上的高k栅介质层。 连接栅极导体形成在高k栅介质层的第一部分和第二部分上。 连接栅极导体从隔离区域上的第一导电器件区域延伸到第二导电器件区域。 然后可以将第一导电器件区域和第二导电器件区域中的一个暴露于含氧气氛中。 用含氧气氛曝光改变暴露的半导体器件的阈值电压。

公开(公告)号：US20150255295A1

公开(公告)日：2015-09-10

申请号：US14197790

申请日：2014-03-05

Applicant: GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Bruce Doris ,  Kangguo Cheng ,  Nicolas Loubet

IPC: H01L21/28 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L29/045 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853

Abstract: One illustrative method disclosed herein involves, among other things, forming trenches to form an initial fin structure having an initial exposed height and sidewalls, forming a protection layer on at least the sidewalls of the initial fin structure, extending the depth of the trenches to thereby define an increased-height fin structure, with a layer of insulating material over-filling the final trenches and with the protection layer in position, performing a fin oxidation thermal anneal process to convert at least a portion of the increased-height fin structure into an isolation material, removing the protection layer, and performing an epitaxial deposition process to form a layer of semiconductor material on at least portions of the initial fin structure.

Abstract translation: 本文中公开的一种说明性方法包括形成沟槽以形成具有初始暴露高度和侧壁的初始鳍结构，在至少初始鳍结构的侧壁上形成保护层，从而延伸沟槽的深度，从而 限定一个增加高度的翅片结构，其中绝缘材料层覆盖最终的沟槽并且将保护层置于适当位置，执行翅片氧化热退火工艺以将至少一部分高度翅片结构转换为 隔离材料，去除保护层，以及进行外延沉积工艺以在初始鳍结构的至少部分上形成半导体材料层。

公开(公告)号：US09117875B2

公开(公告)日：2015-08-25

申请号：US14155499

申请日：2014-01-15

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Kangguo Cheng ,  Bruce Doris ,  Kern Rim

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/306 ,  H01L21/324

CPC classification number: H01L21/76224 ,  H01L21/02532 ,  H01L21/3083 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: Forming a plurality of initial trenches that extend through a layer of silicon-germanium and into a substrate to define an initial fin structure comprised of a portion of the layer of germanium-containing material and a first portion of the substrate, forming sidewall spacers adjacent the initial fin structure, performing an etching process to extend the initial depth of the initial trenches, thereby forming a plurality of final trenches having a final depth that is greater than the initial depth and defining a second portion of the substrate positioned under the first portion of the substrate, forming a layer of insulating material over-filling the final trenches and performing a thermal anneal process to convert at least a portion of the first or second portions of the substrate into a silicon dioxide isolation material that extends laterally under an entire width of the portion of the germanium-containing material.

Abstract translation: 形成多个初始沟槽，其延伸穿过硅 - 锗层并进入衬底以限定由锗含量材料层的一部分和衬底的第一部分组成的初始鳍结构，形成邻近 初始鳍结构，执行蚀刻处理以延长初始沟槽的初始深度，由此形成多个最终深度大于初始深度的最终沟槽，并且限定位于第一部分第一部分下方的衬底的第二部分 所述衬底形成覆盖所述最终沟槽的绝缘材料层，并执行热退火工艺，以将所述衬底的所述第一或第二部分的至少一部分转化成二氧化硅隔离材料，所述二氧化硅隔离材料横向延伸在整个宽度 含锗材料的一部分。

公开(公告)号：US20150200128A1

公开(公告)日：2015-07-16

申请号：US14155499

申请日：2014-01-15

Applicant: International Business Machines Corporation ,  Globalfoundries Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Kangguo Cheng ,  Bruce Doris ,  Kern Rim

IPC: H01L21/762 ,  H01L21/324 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L21/8234

CPC classification number: H01L21/76224 ,  H01L21/02532 ,  H01L21/3083 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: Forming a plurality of initial trenches that extend through a layer of silicon-germanium and into a substrate to define an initial fin structure comprised of a portion of the layer of germanium-containing material and a first portion of the substrate, forming sidewall spacers adjacent the initial fin structure, performing an etching process to extend the initial depth of the initial trenches, thereby forming a plurality of final trenches having a final depth that is greater than the initial depth and defining a second portion of the substrate positioned under the first portion of the substrate, forming a layer of insulating material over-filling the final trenches and performing a thermal anneal process to convert at least a portion of the first or second portions of the substrate into a silicon dioxide isolation material that extends laterally under an entire width of the portion of the germanium-containing material.

Abstract translation: 形成多个初始沟槽，其延伸穿过硅 - 锗层并进入衬底以限定由锗含量材料层的一部分和衬底的第一部分组成的初始鳍结构，形成邻近 初始鳍结构，执行蚀刻处理以延长初始沟槽的初始深度，由此形成多个最终深度大于初始深度的最终沟槽，并且限定位于第一部分第一部分下方的衬底的第二部分 所述衬底形成覆盖所述最终沟槽的绝缘材料层，并执行热退火工艺，以将所述衬底的所述第一或第二部分的至少一部分转化成二氧化硅隔离材料，所述二氧化硅隔离材料横向延伸在整个宽度 含锗材料的一部分。

公开(公告)号：US09064890B1

公开(公告)日：2015-06-23

申请号：US14223545

申请日：2014-03-24

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/66545 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/785

Abstract: One method disclosed includes, among other things, forming an initial fin, covering a top surface and a portion of the sidewalls of the initial fin structure with etch stop material, forming a sacrificial gate structure above and around the initial fin structure, forming a sidewall spacer adjacent the sacrificial gate structure, performing at least one process operation to remove the sacrificial gate structure and thereby define a replacement gate cavity, performing at least one etching process through the replacement gate cavity to remove a portion of the initial fin structure so as to thereby define a final fin structure and a channel cavity positioned below the final fin structure, and substantially filling the channel cavity with an insulating material.

Abstract translation: 公开的一种方法包括形成初始翅片，用蚀刻停止材料覆盖初始翅片结构的顶表面和一部分侧壁，在初始翅片结构的上方和周围形成牺牲栅结构，形成侧壁 邻近牺牲栅极结构的间隔件，执行至少一个处理操作以去除牺牲栅极结构，从而限定替换栅极腔，通过替代栅极腔执行至少一个蚀刻工艺以去除初始鳍结构的一部分，从而 从而限定最终翅片结构和位于最终翅片结构下方的通道腔，并且用绝缘材料基本上填充通道腔。