公开(公告)号：US06893920B2

公开(公告)日：2005-05-17

申请号：US10243791

申请日：2002-09-12

Applicant: Zhong Dong ,  Chuck Jang

Inventor： Zhong Dong ,  Chuck Jang

IPC: H01L21/28 ,  H01L21/314 ,  H01L21/336 ,  H01L29/51 ,  H01L21/8247

CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L21/3144 ,  H01L21/3145 ,  H01L29/511 ,  H01L29/66825

Abstract: A thin buffer layer of SiON is formed on the top surface of the floating gate, in order to protect the polysilicon surface from attack by atomic chlorine produced during the formation of the high temperature oxide of the ONO stack. The buffer layer can also be formed on other dielectric surfaces which are otherwise subject to adverse conditions in subsequent processing, such as the nitride layer in the ONO dielectric stack.

Abstract translation: 在浮栅的顶表面上形成有薄的缓冲层SiON，以便保护多晶硅表面免受在ONO堆叠的高温氧化物形成过程中产生的原子氯的侵蚀。 缓冲层也可以形成在其它电介质表面上，否则在后续处理中会受到不利条件的影响，例如ONO电介质叠层中的氮化物层。

公开(公告)号：US06885044B2

公开(公告)日：2005-04-26

申请号：US10632007

申请日：2003-07-30

Applicant: Yi Ding

Inventor： Yi Ding

IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792 ,  H01L27/10 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/82

CPC classification number: H01L27/11526 ,  G11C16/0458 ,  H01L27/105 ,  H01L27/11543 ,  H01L27/11546 ,  H01L29/7887 ,  H01L29/7923 ,  Y10S257/905 ,  Y10S257/909 ,  Y10S257/92

Abstract: In a nonvolatile memory array in which each cell (110) has two floating gates (160), for any two consecutive memory cells, one source/drain region (174) of one of the cells and one source/drain region of the other one of the cells are provided by a contiguous region of the appropriate conductivity type (e.g. N type) formed in a semiconductor substrate (120). Each such contiguous region provides source/drain regions to only two of the memory cells in that column. The bitlines (180) overlie the semiconductor substrate in which the source/drain regions are formed. The bitlines are connected to the source/drain regions.

Abstract translation: 在其中每个单元（110）具有两个浮动栅极（160）的非易失性存储器阵列中，对于任何两个连续的存储单元，一个单元的一个源极/漏极区域（174）和另一个单元的一个源极/漏极区域 的单元由形成在半导体衬底（120）中的适当导电类型（例如N型）的连续区域提供。 每个这样的连续区域仅向该列中的两个存储单元提供源极/漏极区域。 位线（180）覆盖其中形成源极/漏极区域的半导体衬底。 位线连接到源极/漏极区域。

公开(公告)号：US06881524B2

公开(公告)日：2005-04-19

申请号：US10306397

申请日：2002-11-27

Applicant: John Cauchi ,  Eric Lou

Inventor： John Cauchi ,  Eric Lou

IPC: G03F7/20 ,  G03F9/00

CPC classification number: G03F7/70466

Abstract: A photoresist exposure process is disclosed which produces features which are substantially smaller than the aperture dimension of the mask used to make the feature. The smaller feature size results from a double exposure of the photoresist, combined with a double baking process to create the features in the photoresist. The double baking process thins the layer of photoresist, prior to the second exposure, thereby improving the resolution of the mark created by the second exposure on the photoresist. The process also uses a binary bias mask through which the first exposure is made, which overlaps with the area of the second exposure, to allow a process tolerance for the realignment of the mask over the wafer for the second exposure.

Abstract translation: 公开了一种光刻胶曝光工艺，其产生的特征基本上小于用于制造该特征的掩模的孔径尺寸。 较小的特征尺寸来自光致抗蚀剂的双重曝光，结合双重烘烤工艺以产生光致抗蚀剂中的特征。 双次烘烤处理在第二次曝光之前使光致抗蚀剂层沉淀，从而提高由光致抗蚀剂上的第二次曝光产生的标记的分辨率。 该过程还使用二元偏置掩模，通过该二值偏置掩模进行第一曝光，其与第二曝光的区域重叠，以允许用于第二次曝光的晶片上的掩模重新对准的处理公差。

公开(公告)号：US20050079680A1

公开(公告)日：2005-04-14

申请号：US10962473

申请日：2004-10-13

Applicant: Hsi-Chieh Chen ,  James Shyu ,  Hippo Wu

Inventor： Hsi-Chieh Chen ,  James Shyu ,  Hippo Wu

IPC: H01L21/20 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/1087 ,  H01L27/10829 ,  H01L29/66181

Abstract: A method of forming a trench capacitor is disclosed. After completion of the bottom electrode of the capacitor, a collar dielectric layer is directly formed on the sidewall of the deep trench using self-starved atomic layer chemical vapor deposition (self-starved ALCVD). Then, a high dielectric constant (high k) dielectric layer is formed overlying the collar dielectric and the bottom portion of the deep trench using atomic layer chemical vapor deposition (ALCVD). Thereafter, a conductive layer is filled into the deep trench and recessed to a predetermined depth. A portion of the dielectric layer and the high dielectric constant (high k) layer at the top of the deep trench are removed to complete the fabrication of the deep trench capacitor.

Abstract translation: 公开了一种形成沟槽电容器的方法。 在电容器的底部电极完成之后，使用自匮乏的原子层化学气相沉积（自我饥饿的ALCVD）直接在深沟槽的侧壁上形成环形电介质层。 然后，使用原子层化学气相沉积（ALCVD），在轴环电介质和深沟槽的底部上形成高介电常数（高k）电介质层。 此后，将导电层填充到深沟槽中并凹进到预定深度。 去除深沟槽顶部的介电层和高介电常数（高k）层的一部分，以完成深沟槽电容器的制造。

公开(公告)号：US20050062100A1

公开(公告)日：2005-03-24

申请号：US10986877

申请日：2004-11-15

Applicant: Yung-Hsien Wu ,  Cheng-Che Lee

Inventor： Yung-Hsien Wu ,  Cheng-Che Lee

IPC: H01L21/314 ,  H01L21/318 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/792 ,  H01L29/76 ,  H01L31/062

CPC classification number: H01L21/02326 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02337 ,  H01L21/3144 ,  H01L21/3185 ,  H01L27/10835 ,  H01L27/1087 ,  H01L29/66181

Abstract: A capacitor dielectric structure of a deep trench capacitor for a DRAM cell. A semiconductor silicon substrate is provided wit a deep trench. Silicon nitride deposition is used to form a silicon nitride layer on the sidewall and bottom of the deep trench. An oxynitride process with wet oxidation and N2O reactive gas is used to form an oxynitride layer on the silicon nitride layer. A post oxynitride growth annealing is performed on the oxynitride layer.

Abstract translation: 用于DRAM单元的深沟槽电容器的电容器电介质结构。 半导体硅衬底具有深沟槽。 氮化硅沉积用于在深沟槽的侧壁和底部上形成氮化硅层。 使用具有湿氧化和N2O反应气体的氧氮化物工艺在氮化硅层上形成氧氮化物层。 在氧氮化物层上进行氧氮化后生长退火。

公开(公告)号：US06849529B2

公开(公告)日：2005-02-01

申请号：US10327043

申请日：2002-12-24

Applicant: Yueh-Chuan Lee ,  Shih-Lung Chen

Inventor： Yueh-Chuan Lee ,  Shih-Lung Chen

IPC: H01L21/334 ,  H01L21/8242 ,  H01L29/94 ,  H01L21/38

CPC classification number: H01L27/1087 ,  H01L29/66181 ,  H01L29/945 ,  Y10S438/923

Abstract: A method for manufacturing a trench capacitor that includes providing a semiconductor substrate, forming a deep trench in the substrate, forming a thin sacrificial layer on a surface of the trench, and forming a hemispherical silicon grain layer over the thin sacrificial layer, wherein the sacrificial layer has a thickness to act as an etch stop during a subsequent step to remove at least a portion of the hemispherical silicon grain layer, and is electrically conductive.

公开(公告)号：US06844586B2

公开(公告)日：2005-01-18

申请号：US10803599

申请日：2004-03-17

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11529

Abstract: In a nonvolatile memory, one or more peripheral transistor gates are formed from the same layer (140) as the select gate. The gate dielectric (130) for these peripheral transistors and the gate dielectric (130) for the select gates are formed simultaneously. In a nonvolatile memory, the gate dielectric (130) for the peripheral transistors and the gate dielectric (130) for the select gates (140) have the same thickness. Portions of the control gates (170) overlie the select gates.

公开(公告)号：US20040224503A1

公开(公告)日：2004-11-11

申请号：US10779634

申请日：2004-02-18

Applicant: ProMos Technologies, Inc.

Inventor： Cheng-ta Wu ,  Chang-Cheng Chen ,  Chun-Chi Chen

IPC: H01L021/44

CPC classification number: B01D53/34 ,  B01D45/08 ,  B01D53/74 ,  B01J8/0065 ,  B01J12/00

Abstract: A system for processing residual gas that includes a chamber having at least one baffle for increasing gas flow path, a residual gas inlet mechanism connected to the chamber for supplying residual gas to the chamber, at least one first gas inlet mechanism connected to the chamber for supplying inert gas to the chamber, at least one second gas inlet mechanism connected to the chamber for supplying a reactive gas to the chamber, and a gas outlet mechanism for connected to the chamber for outputting mixed gases from mixing the residual gas, inert gas and reactive gas and non-reacted residual gas, inert gas and reactive gas.

公开(公告)号：US20040178174A1

公开(公告)日：2004-09-16

申请号：US10600699

申请日：2003-06-23

Applicant: ProMos Technologies, Inc.

Inventor： Yung Hsien Wu

IPC: C23F001/00

CPC classification number: H01L21/823462 ,  H01L21/28167 ,  H01L21/28202 ,  H01L21/3185 ,  H01L29/518

Abstract: A method of manufacturing a semiconductor device includes providing a wafer substrate having a surface, forming a first nitride layer over the wafer substrate, providing a layer of photoresist over the first nitride layer, patterning and defining the photoresist layer, etching the first nitride layer unmasked by the photoresist to remove at least a portion of the first nitride layer to expose at least a portion of the substrate surface, removing the photoresist layer, and depositing a second nitride layer over the first nitride layer and the exposed substrate surface to form a nitride structure having a first thickness and a second thickness, wherein the first thickness includes a thickness of the first nitride layer.

Abstract translation: 制造半导体器件的方法包括提供具有表面的晶片衬底，在晶片衬底上形成第一氮化物层，在第一氮化物层上提供一层光致抗蚀剂，图案化和限定光致抗蚀剂层，蚀刻第一氮化物层未屏蔽 通过所述光致抗蚀剂去除所述第一氮化物层的至少一部分以暴露所述衬底表面的至少一部分，去除所述光致抗蚀剂层，以及在所述第一氮化物层和所述暴露的衬底表面上沉积第二氮化物层以形成氮化物 结构具有第一厚度和第二厚度，其中第一厚度包括第一氮化物层的厚度。

公开(公告)号：US20030143849A1

公开(公告)日：2003-07-31

申请号：US10393975

申请日：2003-03-24

Applicant: ProMos Technologies Inc.

Inventor： Ming-Cheng Yang ,  Jiun-Fang Wang

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L21/3212 ,  H01L21/76829 ,  H01L21/7684

Abstract: A method for avoiding defects produced in The CMP process has the following steps: sequentially depositing a first dielectric layer and a second dielectric layer on a semiconductor substrate, wherein the wet-etching rate of the first dielectric layer is greater than the wet-etching rate of the second dielectric layer; forming a plurality of first holes on a plurality of the predetermined contact window areas respectively; wet etching the first dielectric layer in each of the first holes to form a plurality of second holes on the plurality of the predetermined contact window areas respectively; forming a conductive layer to fill each of the second holes; and performing the CMP process to level off the conductive layer and the second dielectric layer.