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公开(公告)号：US20130032793A1
公开(公告)日：2013-02-07
申请号：US13367061
申请日：2012-02-06
Applicant: Do-Hyun KIM , Yoon Ho KHANG , Dong-Hoon LEE , Sang Ho PARK , Se Hwan YU , Cheol Kyu KIM , Yong-Su LEE , Sung-Haeng CHO , Chong Sup CHANG , Dong Jo KIM , Jung Kyu LEE
Inventor： Do-Hyun KIM , Yoon Ho KHANG , Dong-Hoon LEE , Sang Ho PARK , Se Hwan YU , Cheol Kyu KIM , Yong-Su LEE , Sung-Haeng CHO , Chong Sup CHANG , Dong Jo KIM , Jung Kyu LEE
IPC: H01L29/786 , H01L21/20
CPC classification number: H01L27/124 , H01L27/1225 , H01L27/1237 , H01L27/1262 , H01L27/127 , H01L27/1288 , H01L29/45 , H01L29/7869
Abstract: Provided is a thin film transistor array panel. The thin film transistor array panel according to exemplary embodiments of the present invention includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy.
Abstract translation: 提供了一种薄膜晶体管阵列面板。 根据本发明的示例性实施例的薄膜晶体管阵列面板包括：设置在基板上的栅极布线层; 设置在所述栅极布线层上的氧化物半导体层; 以及数据布线层，其设置在所述氧化物半导体层上，所述数据布线层包括包含铜的主布线层和设置在所述主布线层上并包括铜合金的覆盖层。
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公开(公告)号：US08116125B2
公开(公告)日：2012-02-14
申请号：US12081451
申请日：2008-04-16
Applicant: Cheol-kyu Kim , Yoon-ho Khang , Ki-joon Kim
Inventor： Cheol-kyu Kim , Yoon-ho Khang , Ki-joon Kim
CPC classification number: G11C11/5678 , G11C13/0004
Abstract: A method of operating a phase-change memory device, including a phase-change layer and a unit applying a voltage to the phase-change layer, which includes applying a reset voltage to the phase-change layer, wherein the reset voltage includes at least two pulse voltages which are continuously applied.
Abstract translation: 一种操作相变存储器件的方法，包括相变层和向相变层施加电压的单元，其包括向相变层施加复位电压，其中复位电压至少包括 连续施加的两个脉冲电压。
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23.发明申请METHOD FABRICATING NITRIDE-BASED COMPOUND LAYER, GaN SUBSTRATE AND VERTICAL STRUCTURE NITRIDE-BASED SEMICONDUCTOR LIGHT EMITTING DEVICE 有权方法制备基于氮化物的化合物层，GaN衬底和基于硝酸的垂直结构的半导体发光器件公开(公告)号：US20090258453A1
公开(公告)日：2009-10-15
申请号：US12489819
申请日：2009-06-23
Applicant: Soo Min LEE , Cheol Kyu KIM , Jaeun YOO , Sung Hwan JANG , Masayoshi KOIKE
Inventor： Soo Min LEE , Cheol Kyu KIM , Jaeun YOO , Sung Hwan JANG , Masayoshi KOIKE
IPC: H01L33/00
CPC classification number: H01L33/0075 , H01L21/02002 , H01L21/02389 , H01L21/02439 , H01L21/02472 , H01L21/02483 , H01L21/0254 , H01L21/02639 , H01L21/02647 , H01L33/0079
Abstract: In a method for fabricating a nitride-based compound layer, first, a GaN substrate is prepared. A mask layer with a predetermined pattern is formed on the GaN substrate to expose a partial area of the GaN substrate. Then a buffer layer is formed on the partially exposed GaN substrate. The buffer layer is made of a material having a 10% or less lattice mismatch with GaN. Thereafter, the nitride-based compound is grown laterally from a top surface of the buffer layer toward a top surface of the mask layer and the nitride-based compound layer is vertically grown to a predetermined thickness. Also, the mask layer and the buffer layer are removed via wet-etching to separate the nitride-based compound layer from the GaN substrate.
Abstract translation: 在制造氮化物类化合物层的方法中，首先制备GaN衬底。 在GaN衬底上形成具有预定图案的掩模层，以暴露GaN衬底的部分区域。 然后在部分曝光的GaN衬底上形成缓冲层。 缓冲层由具有10％以下与GaN的晶格失配的材料制成。 此后，氮化物类化合物从缓冲层的顶表面朝向掩模层的顶表面横向生长，并且氮化物基化合物层垂直生长至预定厚度。 此外，通过湿蚀刻除去掩模层和缓冲层，以将氮化物基化合物层与GaN衬底分离。
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24.发明授权Method of fabricating nitride-based compound layer, GaN substrate and vertical structure nitride-based semiconductor light emitting device 有权氮化物系化合物层的制造方法，GaN衬底和垂直结构氮化物系半导体发光元件公开(公告)号：US07569461B2
公开(公告)日：2009-08-04
申请号：US11471697
申请日：2006-06-21
Applicant: Soo Min Lee , Cheol Kyu Kim , Jaeun Yoo , Sung Hwan Jang , Masayoshi Koike
Inventor： Soo Min Lee , Cheol Kyu Kim , Jaeun Yoo , Sung Hwan Jang , Masayoshi Koike
IPC: H01L21/20
CPC classification number: H01L33/0075 , H01L21/02002 , H01L21/02389 , H01L21/02439 , H01L21/02472 , H01L21/02483 , H01L21/0254 , H01L21/02639 , H01L21/02647 , H01L33/0079
Abstract: In a method for fabricating a nitride-based compound layer, first, a GaN substrate is prepared. A mask layer with a predetermined pattern is formed on the GaN substrate to expose a partial area of the GaN substrate. Then a buffer layer is formed on the partially exposed GaN substrate. The buffer layer is made of a material having a 10% or less lattice mismatch with GaN. Thereafter, the nitride-based compound is grown laterally from a top surface of the buffer layer toward a top surface of the mask layer and the nitride-based compound layer is vertically grown to a predetermined thickness. Also, the mask layer and the buffer layer are removed via wet-etching to separate the nitride-based compound layer from the GaN substrate.
Abstract translation: 在制造氮化物类化合物层的方法中，首先制备GaN衬底。 在GaN衬底上形成具有预定图案的掩模层，以暴露GaN衬底的部分区域。 然后在部分曝光的GaN衬底上形成缓冲层。 缓冲层由具有10％以下与GaN的晶格失配的材料制成。 此后，氮化物类化合物从缓冲层的顶表面朝向掩模层的顶表面横向生长，并且氮化物基化合物层垂直生长至预定厚度。 此外，通过湿蚀刻除去掩模层和缓冲层，以将氮化物基化合物层与GaN衬底分离。
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Patent Agency Ranking
公开(公告)号：US20090141546A1
公开(公告)日：2009-06-04
申请号：US12081451
申请日：2008-04-16
Applicant: Cheol-kyu Kim , Yoon-ho Khang , Ki-joon Kim
Inventor： Cheol-kyu Kim , Yoon-ho Khang , Ki-joon Kim
IPC: G11C11/00
CPC classification number: G11C11/5678 , G11C13/0004
Abstract: A method of operating a phase-change memory device including a phase-change layer and a unit applying a voltage to the phase-change layer is provided. The method includes applying a reset voltage to the phase-change layer, wherein the reset voltage includes at least two pulse voltages which are continuously applied.
Abstract translation: 提供一种操作包括相变层和向相变层施加电压的单元的相变存储器件的方法。 该方法包括将复位电压施加到相变层，其中复位电压包括连续施加的至少两个脉冲电压。
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公开(公告)号：US07807989B2
公开(公告)日：2010-10-05
申请号：US12213234
申请日：2008-06-17
Applicant: Tae-yon Lee , Ki-joon Kim , Jun-ho Lee , Cheol-kyu Kim
Inventor： Tae-yon Lee , Ki-joon Kim , Jun-ho Lee , Cheol-kyu Kim
IPC: H01L29/02 , H01L21/336
CPC classification number: H01L45/1233 , H01L45/06 , H01L45/148
Abstract: Provided is a phase-change memory using a single-element semimetallic thin film. The device includes a storage node having a phase-change material layer and a switching element connected to the storage node, wherein the storage node includes a single-element semimetallic thin film which is formed between an upper electrode and a lower electrode. Thus, the write speed of the phase-change memory can be increased compared with the case of a Ge—Sb—Te (GST) based material.
Abstract translation: 提供了使用单元件半金属薄膜的相变存储器。 该装置包括具有相变材料层和连接到存储节点的开关元件的存储节点，其中存储节点包括形成在上电极和下电极之间的单元件半金属薄膜。 因此，与基于Ge-Sb-Te（GST）的材料的情况相比，可以提高相变存储器的写入速度。
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27.发明申请NITRIDE SEMICONDUCTOR SINGLE CRYSTAL SUBSTRATE, AND METHODS OF FABRICATING THE SAME AND A VERTICAL NITRIDE SEMICONDUCTOR LIGHT EMITTING DIODE USING THE SAME 有权氮化物半导体单晶衬底，及其制造方法和使用其的垂直氮化物半导体发光二极管的方法公开(公告)号：US20100105159A1
公开(公告)日：2010-04-29
申请号：US12648787
申请日：2009-12-29
Applicant: Cheol Kyu KIM , Yung Ho Ryu , Soo Min Lee , Jong In Yang , Tae Hyung Kim
Inventor： Cheol Kyu KIM , Yung Ho Ryu , Soo Min Lee , Jong In Yang , Tae Hyung Kim
CPC classification number: H01L29/2003 , H01L21/0237 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L21/02576 , H01L21/0262 , H01L21/02664 , H01L33/0075
Abstract: A nitride semiconductor single crystal substrate, a manufacturing method thereof and a method for manufacturing a vertical nitride semiconductor device using the same. According to an aspect of the invention, in the nitride semiconductor single crystal substrate, upper and lower regions are divided along a thickness direction, the nitride single crystal substrate having a thickness of at least 100 μm. Here, the upper region has a doping concentration that is five times or greater than that of the lower region. Preferably, a top surface of the substrate in the upper region has Ga polarity. Also, according to a specific embodiment of the invention, the lower region is intentionally un-doped and the upper region is n-doped. Preferably, each of the upper and lower regions has a doping concentration substantially identical in a thickness direction.
Abstract translation: 氮化物半导体单晶衬底，其制造方法和使用其的垂直氮化物半导体器件的制造方法。 根据本发明的一个方面，在氮化物半导体单晶衬底中，沿着厚度方向分割上部和下部区域，所述氮化物单晶衬底的厚度至少为100μm。 这里，上部区域的掺杂浓度为下部区域的5倍以上。 优选地，上部区域中的基板的顶表面具有Ga极性。 此外，根据本发明的具体实施例，下部区域有意地未掺杂，并且上部区域是n掺杂的。 优选地，上部区域和下部区域中的每一个具有在厚度方向上基本相同的掺杂浓度。
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28.发明申请Storage node, phase change memory device and methods of manufacturing and operating the same 审中-公开存储节点，相变存储器件及其制造和操作方法公开(公告)号：US20090173927A1
公开(公告)日：2009-07-09
申请号：US12232961
申请日：2008-09-26
Applicant: Cheol-kyu Kim , Min-ho Kwon , Yoon-ho Khang , Youn-seon Kang , Tae-yon Lee , Sung Heo , Ki-bum Kim , Sung-wook Nam , Dong-bok Lee
Inventor： Cheol-kyu Kim , Min-ho Kwon , Yoon-ho Khang , Youn-seon Kang , Tae-yon Lee , Sung Heo , Ki-bum Kim , Sung-wook Nam , Dong-bok Lee
CPC classification number: H01L45/126 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/16
Abstract: Provided are a storage node, phase change memory device and methods of manufacturing and operating the same. The storage node may include an electrode, a phase change layer, and an anti-diffusion layer between the electrode and the phase change layer and including a silicide compound. The phase change memory device may include the storage node and a switching device connected to the storage node.
Abstract translation: 提供了一种存储节点，相变存储器件及其制造和操作方法。 存储节点可以包括在电极和相变层之间的电极，相变层和抗扩散层，并且包括硅化物化合物。 相变存储器件可以包括存储节点和连接到存储节点的交换设备。
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公开(公告)号：US07042796B2
公开(公告)日：2006-05-09
申请号：US10877557
申请日：2004-06-24
Applicant: Cheol-Kyu Kim , Ja-Seung Gou
Inventor： Cheol-Kyu Kim , Ja-Seung Gou
IPC: G11C8/00
Abstract: An apparatus, included in a semiconductor memory device, for generating a bank control signal, includes a logic block for receiving an internal precharge signal and a power-up signal and outputting a first signal; and a latch block for latching an internal active signal and the first signal in order to generate the bank control signal.
Abstract translation: 包括在半导体存储器件中的用于产生存储体控制信号的装置包括用于接收内部预充电信号和上电信号并输出第一信号的逻辑块; 以及用于锁存内部有效信号和第一信号的锁存块，以便产生存储体控制信号。
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