公开(公告)号：US20070111502A1

公开(公告)日：2007-05-17

申请号：US11620541

申请日：2007-01-05

Applicant: Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter

Inventor： Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter

IPC: H01L21/44

CPC classification number: H01L24/12 ,  B23K3/0623 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05017 ,  H01L2224/05546 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05599 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  Y10T29/49144 ,  H01L2224/13099

Abstract: A system and method for forming a novel C4 solder bump for BLM (Ball Limiting Metallurgy) includes a novel damascene technique is implemented to eliminate the Cu undercut problem and improve the C4 pitch. In the process, a barrier layer metal stack is deposited above a metal pad layer. A top layer of the barrier layer metals (e.g., Cu) is patterned by CMP. Only bottom layers of the barrier metal stack are patterned by a wet etching. The wet etch time for the Cu-based metals is greatly reduced resulting in a reduced undercut. This allows the pitch of the C4 solder bumps to be reduced. An alternate method includes use of multiple vias at the solder bump terminal.

Abstract translation: 用于形成用于BLM（Ball Limite Metallurgy）的新型C4焊料凸块的系统和方法包括实现新颖的镶嵌技术以消除Cu底切问题并提高C4间距。 在该过程中，在金属焊盘层上方沉积阻挡层金属堆叠。 通过CMP对阻挡层金属（例如Cu）的顶层进行图案化。 仅通过湿蚀刻图案化阻挡金属叠层的底层。 Cu基金属的湿蚀刻时间大大降低，从而减少了底切。 这样可以减少C4焊料凸点的间距。 一种替代方法包括在焊料凸点端子处使用多个通孔。

公开(公告)号：US20070105359A1

公开(公告)日：2007-05-10

申请号：US11164107

申请日：2005-11-10

Applicant: Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter

Inventor： Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter

IPC: H01L21/44

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/11912 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2224/05552

Abstract: An electrical interconnection structure and method for forming. The electrical structure comprises a substrate comprising electrically conductive pads and a first dielectric layer over the substrate and the electrically conductive pads. The first dielectric layer comprises vias. A metallic layer is formed over the first dielectric layer and within the vias. A second dielectric layer is formed over the metallic layer. A ball limiting metallization layer is formed within the vias. A photoresist layer is formed over a surface of the ball limiting metallization layer. A first solder ball is formed within a first opening in the photoresist layer and a second solder ball is formed within a second opening in the photoresist layer.

Abstract translation: 电互连结构及其形成方法。 该电气结构包括一个衬底，该衬底包括导电焊盘和该衬底上的第一介电层和该导电焊盘。 第一介电层包括通孔。 金属层形成在第一介电层之上和通孔内。 第二电介质层形成在金属层上。 在通孔内形成球限制金属化层。 在球限制金属化层的表面上形成光致抗蚀剂层。 在光致抗蚀剂层的第一开口内形成第一焊球，在光致抗蚀剂层的第二开口内形成第二焊球。

公开(公告)号：US20070051875A1

公开(公告)日：2007-03-08

申请号：US11161941

申请日：2005-08-23

Applicant: Fen Chen ,  Richard Kontra ,  Tom Lee ,  Theodore Levin ,  Christopher Muzzy ,  Timothy Sullivan

Inventor： Fen Chen ,  Richard Kontra ,  Tom Lee ,  Theodore Levin ,  Christopher Muzzy ,  Timothy Sullivan

IPC: H01J40/14 ,  H01L31/00

CPC classification number: G11C13/0009 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/04 ,  G11C13/047 ,  G11C2013/0054 ,  H01L45/1213 ,  H01L45/145

Abstract: A structure and a method for operating the same. The method comprises providing a resistive/reflective region on a substrate, wherein the resistive/reflective region comprises a material having a characteristic of changing the material's reflectance due to the material absorbing heat; sending an electric current through the resistive/reflective region so as to cause a reflectance change in the resistive/reflective region from a first reflectance value to a second reflectance value different from the first reflectance value; and optically reading the reflectance change in the resistive/reflective region.

Abstract translation: 一种结构及其操作方法。 该方法包括在衬底上提供电阻/反射区域，其中电阻/反射区域包括具有由于材料吸收热而改变材料的反射率的特性的材料; 发送电流通过电阻/反射区域，以使电阻/反射区域的反射率变化从第一反射率值到不同于第一反射率值的第二反射率值; 并且光学地读取电阻/反射区域中的反射率变化。

公开(公告)号：US20060292830A1

公开(公告)日：2006-12-28

申请号：US11463348

申请日：2006-08-09

Applicant: Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter

Inventor： Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter

IPC: H01L21/00

CPC classification number: H01L21/78

Abstract: A semiconductor structure and method for chip dicing. The method includes (a) providing a semiconductor substrate and (b) forming first and second device regions in and at top of the substrate. The first and second device regions are separated by a semiconductor border region of the substrate. The method further includes (c) forming N interconnect layers, in turn, directly above the semiconductor border region and the first and second device regions. N is a positive integer greater than one. Each of the N interconnect layers includes an etchable portion directly above the semiconductor border region. The etchable portions of the N interconnect layers form a continuous etchable block directly above the semiconductor border region. The method further includes (d) removing the continuous etchable block by etching, and (e) cutting with a laser through the semiconductor border region via an empty space of the removed continuous etchable block.

Abstract translation: 一种用于芯片切割的半导体结构和方法。 该方法包括（a）提供半导体衬底和（b）在衬底中和顶部形成第一和第二器件区域。 第一和第二器件区域被衬底的半导体边界区域分开。 该方法还包括（c）在半导体边界区域以及第一和第二器件区域的正上方形成N个互连层。 N是大于1的正整数。 N个互连层中的每一个包括直接在半导体边界区域上方的可蚀刻部分。 N互连层的可蚀刻部分在半导体边界区域正上方形成连续的可蚀刻块。 该方法还包括（d）通过蚀刻去除连续可蚀刻块，以及（e）经由去除的连续可蚀刻块的空白空间，通过半导体边界区域用激光切割。

公开(公告)号：US20060281197A1

公开(公告)日：2006-12-14

申请号：US11160154

申请日：2005-06-10

Applicant: Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter ,  Jeffrey Zimmerman

Inventor： Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter ,  Jeffrey Zimmerman

IPC: H01L21/66

CPC classification number: H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and apparatus for determining the complete coverage of a passivating material on the final conductive interconnection of a wafer containing integrated circuits. A test structure with the dimensions of the final interconnections of the integrated circuits is formed during manufacture of the integrated circuits and used to determine complete coverage of the wafer by creating an opening in the passivating material at the test structure, the size of the opening being indicative of the complete coverage of the wafer.

Abstract translation: 一种用于确定包含集成电路的晶片的最终导电互连上的钝化材料的完全覆盖的方法和装置。 在集成电路的制造期间形成具有集成电路的最终互连尺寸的测试结构，并且用于通过在测试结构处在钝化材料中形成开口来确定晶片的完全覆盖，开口的尺寸为 指示晶片的完全覆盖。

公开(公告)号：US20060244139A1

公开(公告)日：2006-11-02

申请号：US10908083

申请日：2005-04-27

Applicant: Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter

Inventor： Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L24/03 ,  H01L23/3171 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05583 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/10126 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: A solder bump structure and method for forming the same. The structure includes (a) a dielectric layer including a dielectric layer top surface (b) an electrically conducting bond pad on and in direct physical contact with the dielectric layer top surface; (c) a patterned support/interface layer on the dielectric layer top surface and thicker than the electrically conducting bond pad in the reference direction, wherein the patterned support/interface layer comprises a hole and a trench, wherein the hole is directly above the electrically conducting bond pad, and wherein the trench is not filled by any electrically conducting material; and (d) an electrically conducting solder bump filling the hole and electrically coupled to the electrically conducting bond pad.

Abstract translation: 一种焊料凸块结构及其形成方法。 该结构包括：（a）介电层，包括电介质层顶表面（b）与电介质层顶表面直接物理接触的导电接合焊盘; （c）在电介质层顶表面上的图案化支撑/界面层，并且比参考方向上的导电接合焊盘厚，其中所述图案化支撑/界面层包括孔和沟槽，其中所述孔直接位于电气 导电接合焊盘，并且其中所述沟槽未被任何导电材料填充; 和（d）填充该孔并电耦合到导电接合焊盘的导电焊料凸块。

公开(公告)号：US20060076159A1

公开(公告)日：2006-04-13

申请号：US10711885

申请日：2004-10-12

Applicant: Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter

Inventor： Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter

IPC: H05K1/11 ,  H01L23/52

CPC classification number: H01L23/544 ,  H01L22/24 ,  H01L22/32 ,  H01L22/34 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/48 ,  H01L2223/5448 ,  H01L2224/02166 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/13099 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49227 ,  H01L2224/45099

Abstract: An integrated circuit has a wiring layer below an insulator layer. A pad comprises a conductive material that is on the insulator layer. The pad has a wirebond connection region and a probe pad region. An inspection mark is between the wirebond connection region and the probe pad region. The inspection mark comprises an opening in the insulator layer that is filled with the conductive material. In addition, a contact that is through the insulator layer is adapted to electrically connect the conductor wire in the wiring layer to the pad. The contact is formed of the same conductive material used for the pad and the inspection mark.

Abstract translation: 集成电路在绝缘体层下方具有布线层。 衬垫包括位于绝缘体层上的导电材料。 焊盘具有引线连接区域和探针焊盘区域。 导线连接区域和探针焊盘区域之间的检查标记。 检查标记包括填充有导电材料的绝缘体层中的开口。 此外，穿过绝缘体层的接触件适于将布线层中的导线电连接到焊盘。 接触由用于垫和检查标记的相同的导电材料形成。