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1.发明授权Method of forming a crack stop laser fuse with fixed passivation layer coverage 有权形成具有固定钝化层覆盖的裂纹停止激光熔丝的方法公开(公告)号：US07704804B2
公开(公告)日：2010-04-27
申请号：US11953363
申请日：2007-12-10
IPC分类号： H01L21/82
CPC分类号： H01L23/5258 , H01L23/585 , H01L24/02 , H01L24/03 , H01L24/12 , H01L2224/03 , H01L2224/0401 , H01L2224/05006 , H01L2224/05572 , H01L2224/13022 , H01L2224/16 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2224/05552
摘要： A crack stop void is formed in a low-k dielectric or silicon oxide layer between adjacent fuse structures for preventing propagation of cracks between the adjacent fuse structures during a fuse blow operation. The passivation layer is fixed in place by using an etch stop shape of conducting material which is formed simultaneously with the formation of the interconnect structure. This produces a reliable and repeatable fuse structure that has controllable passivation layer over the fuse structure that is easily manufactured.
摘要翻译： 在相邻熔丝结构之间的低k电介质或氧化硅层中形成裂纹阻挡空隙，用于在保险丝熔断操作期间防止相邻熔丝结构之间的裂纹传播。 通过使用与形成互连结构同时形成的导电材料的蚀刻停止形状将钝化层固定就位。 这产生了可靠且可重复的熔丝结构，其在容易制造的熔丝结构上具有可控钝化层。
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公开(公告)号：US20070200229A1
公开(公告)日：2007-08-30
申请号：US11276380
申请日：2006-02-27
CPC分类号： H01L21/563 , H01L23/3128 , H01L24/10 , H01L24/13 , H01L24/14 , H01L24/17 , H01L24/29 , H01L24/81 , H01L2224/0401 , H01L2224/0603 , H01L2224/13 , H01L2224/13099 , H01L2224/14 , H01L2224/1403 , H01L2224/14051 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/81194 , H01L2224/8121 , H01L2224/81815 , H01L2224/83194 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/00 , H01L2924/3512
摘要： A semiconductor structure and method for forming the same. The semiconductor structure includes (a) a substrate and (b) a chip which includes N chip solder balls, N is a positive integer, and the N chip solder balls are in electrical contact with the substrate. The semiconductor structure further includes (c) first, second, third, and fourth corner underfill regions which are respectively at first, second, third, and fourth corners of the chip, and sandwiched between the chip and the substrate. The semiconductor structure further includes (d) a main underfill region sandwiched between the chip and the substrate. The first, second, third, and fourth corner underfill regions, and the main underfill region occupy essentially an entire space between the chip and the substrate. A corner underfill material of the first, second, third, and fourth corner underfill regions is different from a main underfill material of the main underfill region.
摘要翻译： 一种半导体结构及其形成方法。 半导体结构包括（a）基板和（b）包括N个芯片焊球，N是正整数的芯片，并且N个芯片焊球与基板电接触。 半导体结构还包括（c）分别在芯片的第一，第二，第三和第四角部处并夹在芯片和基板之间的第一，第二，第三和第四角底部填充区域。 半导体结构还包括（d）夹在芯片和衬底之间的主要底部填充区域。 第一，第二，第三和第四角底部填充区域，并且主底部填充区域基本上占据芯片和基板之间的整个空间。 第一，第二，第三和第四角底部填充区域的角底层填充材料与主要底部填充区域的主要底部填充材料不同。
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公开(公告)号：US20070176288A1
公开(公告)日：2007-08-02
申请号：US11275867
申请日：2006-02-01
IPC分类号： H01L23/48
CPC分类号： H01L24/13 , H01L23/562 , H01L24/11 , H01L2224/05001 , H01L2224/05008 , H01L2224/05024 , H01L2224/05124 , H01L2224/05147 , H01L2224/05572 , H01L2224/056 , H01L2224/13099 , H01L2224/13111 , H01L2224/16 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/15787 , H01L2924/00014 , H01L2924/00
摘要： A structure and method for forming the same. The semiconductor structure includes a first semiconductor chip and N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer. The semiconductor structure also includes a first solder wall on a perimeter of the first semiconductor chip such that the first solder wall forms a closed loop surrounding the N solder bumps.
摘要翻译： 其形成结构及其方法。 半导体结构包括与第一半导体芯片直接物理接触的第一半导体芯片和N个焊料凸块，其中N是正整数。 半导体结构还包括在第一半导体芯片的周边上的第一焊料壁，使得第一焊料壁形成围绕N个焊料凸点的闭环。
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公开(公告)号：US20060076677A1
公开(公告)日：2006-04-13
申请号：US10964495
申请日：2004-10-12
IPC分类号： H01L23/48
CPC分类号： H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/03009 , H01L2224/0347 , H01L2224/03622 , H01L2224/0401 , H01L2224/05572 , H01L2224/1147 , H01L2224/11472 , H01L2224/11906 , H01L2224/13006 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01016 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2224/05552
摘要： A method and system for preventing undercutting of the solder bump in a C4 package by forming a barrier of resist that effectively widens the footprint of the solder bump. The BLM is then etched to the perimeter edge of the barrier rather than the solder bump, thereby precluding any undercutting of the solder bump by the BLM. The barrier may formed by using a half-tone mask that fully exposes the immediately surrounding regions to define a sidewall enclosing the C4 cavity. The barrier may also be formed by applying a second resist prior to, or after, plating the solder and then patterning to inhibit etching directly adjacent to the C4 cavity. The barrier may additionally be formed by overfilling solder into the C4 cavity so that it spreads laterally over the sidewall portion of the resist layer. The resist is then etched anisotropically to leave the barrier. In another embodiment, a taper is introduced into the profile of the C4 cavity by reflowing the resist by an annealing step. The resist is then etched anisotropically to leave the barrier surrounding the C4 solder.
摘要翻译： 一种用于通过形成抗蚀剂屏障来防止C4封装中的焊料凸块的底切的方法和系统，其有效地加宽了焊料凸块的覆盖区。 然后将BLM蚀刻到屏障的周边边缘而不是焊料凸块，从而阻止BLM对焊料凸块的任何底切。 屏障可以通过使用完全暴露紧邻周围区域以限定封闭C4空腔的侧壁的半色调蒙版来形成。 阻挡层也可以通过在电镀之前或之后施加第二抗蚀剂形成，然后形成图案以抑制直接邻近C4腔的蚀刻。 阻挡层可以另外通过将焊料过度填充到C4空腔中形成，使得其在抗蚀剂层的侧壁部分上横向扩展。 然后将抗蚀剂各向异性地蚀刻以离开屏障。 在另一个实施例中，通过退火步骤回流抗蚀剂，将锥形引入到C4空腔的轮廓中。 然后将抗蚀剂各向异性地蚀刻以留下围绕C4焊料的阻挡层。
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5.发明申请METHOD FOR FORMING C4 CONNECTIONS ON INTEGRATED CIRCUIT CHIPS AND THE RESULTING DEVICES 有权用于形成集成电路芯片和结果设备上的C4连接的方法公开(公告)号：US20070252274A1
公开(公告)日：2007-11-01
申请号：US11380215
申请日：2006-04-26
申请人： Timothy Daubenspeck , Mukta Farooq , Jeffrey Gambino , Christopher Muzzy , Kevin Petrarca , Wolfgang Sauter
发明人： Timothy Daubenspeck , Mukta Farooq , Jeffrey Gambino , Christopher Muzzy , Kevin Petrarca , Wolfgang Sauter
CPC分类号： H01L24/03 , H01L23/3192 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02125 , H01L2224/034 , H01L2224/03616 , H01L2224/0391 , H01L2224/0401 , H01L2224/05006 , H01L2224/05018 , H01L2224/05027 , H01L2224/05083 , H01L2224/05124 , H01L2224/05155 , H01L2224/05166 , H01L2224/0517 , H01L2224/05171 , H01L2224/05181 , H01L2224/05184 , H01L2224/05546 , H01L2224/05556 , H01L2224/05559 , H01L2224/05571 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/05671 , H01L2224/113 , H01L2224/11334 , H01L2224/1147 , H01L2224/1148 , H01L2224/11849 , H01L2224/11901 , H01L2224/11902 , H01L2224/13022 , H01L2224/13023 , H01L2224/13024 , H01L2224/13111 , H01L2924/00013 , H01L2924/0002 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/15788 , H01L2924/30107 , H01L2924/00014 , H01L2924/01007 , H01L2924/00015 , H01L2924/00011 , H01L2924/00012 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552 , H01L2924/00
摘要： A method for forming preferably Pb-lead C4 connections or capture pads with ball limiting metallization on an integrated circuit chip by using a damascene process and preferably Cu metallization in the chip and in the ball limiting metallization for compatibility. In two one embodiment, the capture pad is formed in the top insulating layer and it also serves as the final level of metallization in the chip.
摘要翻译： 一种用于在集成电路芯片上形成优选Pb-lead C4连接或具有球限制金属化的捕获焊盘的方法，其通过使用镶嵌工艺并且优选地在芯片中的Cu金属化和用于兼容性的球限制金属化中。 在两个实施例中，捕获垫形成在顶部绝缘层中，并且还用作芯片中金属化的最终级别。
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公开(公告)号：US20070013071A1
公开(公告)日：2007-01-18
申请号：US11160461
申请日：2005-06-24
IPC分类号： H01L23/52
CPC分类号： H01L24/05 , H01L22/32 , H01L22/34 , H01L24/06 , H01L2224/05624 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/14 , H01L2924/00014
摘要： A structure and a method for forming the same. The structure includes (a) a substrate having a top substrate surface; (b) an integrated circuit on the top substrate surface, wherein the integrated circuit includes a bond pad electrically connected to a transistor of the integrated circuit; (c) a protection ring on the top substrate surface and on a perimeter of the integrated circuit; (c) a kerf region on the top substrate surface, wherein the protection ring is sandwiched between and physically isolates the integrated circuit and the kerf region, wherein the kerf region includes a probe pad electrically connected to the bond pad, and wherein the kerf region is adapted to be destroyed by chip dicing without damaging the integrated circuit and the protection ring.
摘要翻译： 一种结构及其形成方法。 该结构包括（a）具有顶部衬底表面的衬底; （b）在顶部衬底表面上的集成电路，其中所述集成电路包括电连接到所述集成电路的晶体管的接合焊盘; （c）在顶部基板表面上和集成电路的周边上的保护环; （c）顶部衬底表面上的切口区域，其中所述保护环夹在所述集成电路和所述切口区域之间并物理隔离所述集成电路和所述切口区域，其中所述切口区域包括电连接到所述接合焊盘的探针焊盘，并且其中所述切口区域 适用于通过芯片切割而损坏，而不会损坏集成电路和保护环。
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公开(公告)号：US20060016861A1
公开(公告)日：2006-01-26
申请号：US10710562
申请日：2004-07-21
IPC分类号： B23K31/02
CPC分类号： H01L24/12 , B23K3/0623 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05006 , H01L2224/05017 , H01L2224/05546 , H01L2224/05556 , H01L2224/05557 , H01L2224/05599 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/11912 , H01L2224/13006 , H01L2224/131 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , Y10T29/49144 , H01L2224/13099
摘要： A system and method for forming a novel C4 solder bump for BLM (Ball Limiting Metallurgy) includes a novel damascene technique is implemented to eliminate the Cu undercut problem and improve the C4 pitch. In the process, a barrier layer metal stack is deposited above a metal pad layer. A top layer of the barrier layer metals (e.g., Cu) is patterned by CMP. Only bottom layers of the barrier metal stack are patterned by a wet etching. The wet etch time for the Cu-based metals is greatly reduced resulting in a reduced undercut. This allows the pitch of the C4 solder bumps to be reduced. An alternate method includes use of multiple vias at the solder bump terminal.
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公开(公告)号：US20080023833A1
公开(公告)日：2008-01-31
申请号：US11869787
申请日：2007-10-10
CPC分类号： H01L24/03 , H01L23/3171 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05023 , H01L2224/05073 , H01L2224/05124 , H01L2224/05558 , H01L2224/05562 , H01L2224/05567 , H01L2224/05568 , H01L2224/05572 , H01L2224/05583 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05671 , H01L2224/10126 , H01L2224/11462 , H01L2224/1147 , H01L2224/1148 , H01L2224/11849 , H01L2224/13007 , H01L2224/13022 , H01L2224/13099 , H01L2224/13111 , H01L2924/0001 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2224/05552
摘要： A solder bump structure and method for forming the same. The structure includes (a) a dielectric layer including a dielectric layer top surface (b) an electrically conductive bond pad on and in direct physical contact with the dielectric layer top surface; (c) a patterned support/interface layer on the dielectric layer top surface and thicker than the electrically conductive bond pad in the reference direction, wherein the patterned support/interface layer includes a hole and a trench, wherein the hole is directly above the electrically conductive bond pad, and wherein the trench is not filled by any electrically conductive material; and (d) an electrically conductive solder bump filling the hole and electrically coupled to the electrically conductive bond pad.
摘要翻译： 一种焊料凸块结构及其形成方法。 该结构包括（a）包括电介质层顶表面的电介质层（b）与电介质层顶表面直接物理接触的导电接合焊盘; （c）电介质层顶表面上的图案化支撑/界面层，并且在参考方向上比导电接合焊盘厚，其中图案化支撑/界面层包括孔和沟槽，其中孔直接位于电气 导电接合焊盘，并且其中所述沟槽不被任何导电材料填充; 和（d）填充该孔并电耦合到导电接合焊盘的导电焊料凸块。
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公开(公告)号：US20060267136A1
公开(公告)日：2006-11-30
申请号：US10908707
申请日：2005-05-24
IPC分类号： H01L29/00
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： An Integrated Circuit (IC) chip with fused circuits and method of making the IC. Fuses in an upper wiring layer are formed using a multi-tone mask to define rounded bottom corners on the fuses, while wiring in the upper wiring layer maintain a rectangular cross-section.
摘要翻译： 具有融合电路的集成电路（IC）芯片和制造IC的方法。 使用多色调掩模形成上部布线层中的保险丝，以在熔丝上限定圆形的底角，而上部布线层中的布线保持矩形的横截面。
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公开(公告)号：US20060246703A1
公开(公告)日：2006-11-02
申请号：US10908084
申请日：2005-04-27
IPC分类号： H01L21/44
CPC分类号： H01L23/556 , H01L24/02 , H01L24/11 , H01L24/12 , H01L2224/0401 , H01L2224/05572 , H01L2224/13022 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15787 , H01L2924/00 , H01L2924/00014
摘要： A structure and a method for forming the same. The method includes (a) providing a structure which includes (i) a dielectric layer, (ii) an electrically conducting bond pad on and in direct physical contact with the dielectric layer top surface, (iii) a first passivation layer on the dielectric layer top surface and on the electrically conducting bond pad, wherein the first passivation layer comprises a first hole directly above the electrically conducting bond pad, and (iv) an electrically conducting solder bump filling the first hole and electrically coupled to the electrically conducting bond pad; and (b) forming a second passivation layer on the first passivation layer, wherein second passivation layer is in direct physical contact with the electrically conducting solder bump, and wherein the electrically conducting solder bump is exposed to a surrounding ambient immediately after said forming the second passivation layer is performed.
摘要翻译： 一种结构及其形成方法。 该方法包括（a）提供一种结构，其包括（i）电介质层，（ii）与电介质层顶表面直接物理接触的导电接合焊盘，（iii）介电层上的第一钝化层 其中所述第一钝化层包括位于所述导电接合焊盘正上方的第一孔，以及（iv）填充所述第一孔并电耦合到所述导电接合焊盘的导电焊料凸块; 以及（b）在所述第一钝化层上形成第二钝化层，其中第二钝化层与所述导电焊料凸块直接物理接触，并且其中所述导电焊料凸点在所述第二钝化层形成所述第二钝化层之后立即暴露于周围环境 执行钝化层。
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