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21.发明授权公开(公告)号：US06207557B1
公开(公告)日：2001-03-27
申请号：US09356928
申请日：1999-07-19
Applicant: Jang-eun Lee , Ju-hyuck Chung , Tae-wook Seo
Inventor： Jang-eun Lee , Ju-hyuck Chung , Tae-wook Seo
IPC: H01L214763
CPC classification number: H01L21/76856 , H01L21/28556 , H01L21/76843 , H01L21/76846
Abstract: A method of forming a multilayer titanium nitride film hardly containing any Cl component by a multiple step chemical vapor deposition method, and a method of manufacturing a semiconductor device using the same are provided. In the present invention, a multilayer TiN film is formed by multiple step chemical vapor deposition (CVD) on a semiconductor substrate on which an underlayer is formed. In order to form the multilayer TiN film, an underlayer protective TiN film is formed by forming a first TiN film on the underlayer and NH3 annealing the first TiN film. A main TiN film is formed by forming a second TiN film on the underlayer protective TiN film and NH3 annealing the second TiN film. A source gas used in order to form the first TiN film has a smaller TiCl4 to NH3 gas flow ratio than a source gas for forming the second TiN film. In order to apply the multilayer TiN film to the fabrication of the semiconductor device, an insulating film having a contact hole is formed on a semiconductor substrate. A Ti film is formed on the inner wall of the contact hole. A multilayer TiN film is formed on the Ti film by the multiple step CVD method. A metal plug is formed on the multilayer TiN film.
Abstract translation: 提供了通过多步化学气相沉积法形成几乎不含任何Cl成分的多层氮化钛膜的方法，以及制造使用其的半导体器件的方法。 在本发明中，通过在其上形成有底层的半导体衬底上进行多步化学气相沉积（CVD）形成多层TiN膜。 为了形成多层TiN膜，通过在底层上形成第一TiN膜，并对第一TiN膜进行NH 3退火，形成下层保护TiN膜。 通过在底层保护性TiN膜上形成第二TiN膜并使NH 3退火第二TiN膜来形成主TiN膜。 用于形成第一TiN膜的源气体与用于形成第二TiN膜的源气体相比具有较小的TiCl 4与NH 3气体流量比。 为了将多层TiN膜施加到半导体器件的制造中，在半导体衬底上形成具有接触孔的绝缘膜。 在接触孔的内壁上形成有Ti膜。 通过多步CVD法在Ti膜上形成多层TiN膜。 在多层TiN膜上形成金属塞。
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22.发明授权Magnetic tunneling junction devices, memories, memory systems, and electronic devices 有权磁隧道结设备，存储器，存储器系统和电子设备公开(公告)号：US08987798B2
公开(公告)日：2015-03-24
申请号：US14306792
申请日：2014-06-17
Applicant: Jeong Heon Park , Woo Chang Lim , Se Chung Oh , Young Hyun Kim , Sang Hwan Park , Jang Eun Lee
Inventor： Jeong Heon Park , Woo Chang Lim , Se Chung Oh , Young Hyun Kim , Sang Hwan Park , Jang Eun Lee
CPC classification number: H01L43/08 , G06F13/16 , G11C11/161 , G11C11/1659 , H01L43/02 , H01L43/10
Abstract: Provided is a magnetic tunneling junction device including a first structure including a magnetic layer; a second structure including at least two extrinsic perpendicular magnetization structures, each including a magnetic layer and; a perpendicular magnetization inducing layer on the magnetic layer; and a tunnel barrier between the first and second structures.
Abstract translation: 本发明提供一种包括具有磁性层的第一结构的磁性隧道接合装置; 包括至少两个外在垂直磁化结构的第二结构，每个包括磁性层; 磁性层上的垂直磁化诱导层; 以及第一和第二结构之间的隧道屏障。
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公开(公告)号：US20130042081A1
公开(公告)日：2013-02-14
申请号：US13398640
申请日：2012-02-16
Applicant: Jeong Heon Park , Woo Chang Lim , Se Chung Oh , Young Hyun Kim , Sang Hwan Park , Jang Eun Lee
Inventor： Jeong Heon Park , Woo Chang Lim , Se Chung Oh , Young Hyun Kim , Sang Hwan Park , Jang Eun Lee
CPC classification number: H01L43/08 , G06F13/16 , G11C11/161 , G11C11/1659 , H01L43/02 , H01L43/10
Abstract: Provided is a magnetic tunneling junction device including a first structure including a magnetic layer; a second structure including at least two extrinsic perpendicular magnetization structures, each including a magnetic layer and; a perpendicular magnetization inducing layer on the magnetic layer; and a tunnel barrier between the first and second structures.
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24.发明申请RESISTIVE MEMORY DEVICES INCLUDING SELECTED REFERENCE MEMORY CELLS OPERATING RESPONSIVE TO READ OPERATIONS 有权包括选择的参考存储器电容的电阻存储器件操作响应于读操作公开(公告)号：US20110310657A1
公开(公告)日：2011-12-22
申请号：US13219582
申请日：2011-08-26
Applicant: Hyun-Jo Kim , Kyung-Tae Nam , In-Gyu Baek , Se-Chung Oh , Jang-Eun Lee , Jun-Ho Jeong
Inventor： Hyun-Jo Kim , Kyung-Tae Nam , In-Gyu Baek , Se-Chung Oh , Jang-Eun Lee , Jun-Ho Jeong
IPC: G11C11/00
CPC classification number: G11C7/062 , G11C7/067 , G11C7/14 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/0016 , G11C13/004 , G11C2013/0054 , G11C2213/32 , G11C2213/79
Abstract: A Resistance based Random Access Memory (ReRAM) can include a sense amplifier circuit that includes a first input coupled to a bit line of a reference cell in a first block of the ReRAM responsive to a read operation to a second block.
Abstract translation: 基于电阻的随机存取存储器（ReRAM）可以包括读出放大器电路，其响应于对第二块的读取操作，包括耦合到ReRAM的第一块中的参考单元的位线的第一输入。
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公开(公告)号：US08035145B2
公开(公告)日：2011-10-11
申请号：US12773451
申请日：2010-05-04
Applicant: Jun-Soo Bae , Jang-Eun Lee , Hyun-Jo Kim , Se-Chung Oh , Kyung-Tae Nam
Inventor： Jun-Soo Bae , Jang-Eun Lee , Hyun-Jo Kim , Se-Chung Oh , Kyung-Tae Nam
IPC: H01L21/02
CPC classification number: G11C11/15 , B82Y25/00 , B82Y40/00 , H01F10/3254 , H01F10/3272 , H01F10/3281 , H01F41/302 , H01L43/08
Abstract: A magnetic memory device is provided. The magnetic memory device includes an invariable pinning pattern and a variable pinning pattern on a substrate. A tunnel barrier pattern is interposed between the invariable pinning pattern and the variable pinning pattern, and the pinned pattern is interposed between the invariable pinning pattern and the tunnel barrier pattern. A storage free pattern is interposed between the tunnel barrier pattern and the variable pinning pattern, and a guide free pattern is interposed between the storage free pattern and the variable pinning pattern. A free reversing pattern is interposed between the storage and guide free patterns. The free reversing pattern reverses a magnetization direction of the storage free pattern and a magnetization direction of the guide free pattern in the opposite directions.
Abstract translation: 提供磁存储器件。 磁存储器件在衬底上包括不变的钉扎图案和可变的钉扎图案。 在不变的钉扎图案和可变钉扎图案之间插入隧道势垒图案，并且钉扎图案介于不变钉扎图案和隧道屏障图案之间。 在隧道势垒图案和可变钉扎图案之间插入无存储图案，并且在存储空闲图案和可变钉扎图案之间插入无引导图案。 在存储和无引导模式之间插入一个自由的反转模式。 自由反转图案反转无存储图案的磁化方向和反向自由图案的磁化方向。
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Patent Agency Ranking
26.发明授权Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same 有权具有相变存储单元的半导体器件，使用该半导体器件的电子系统及其制造方法公开(公告)号：US08026543B2
公开(公告)日：2011-09-27
申请号：US12338814
申请日：2008-12-18
Applicant: Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
Inventor： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
IPC: H01L27/108 , H01L47/00
CPC classification number: H01L29/7843 , H01L27/2436 , H01L29/665 , H01L29/7833 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1666 , H01L45/1675
Abstract: A phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation. In one embodiment, a semiconductor memory device includes a molding layer disposed over semiconductor substrate, a phase-changeable material pattern, and an oxidation barrier of electrically insulative material. The molding layer has a protrusion at its upper portion. One portion of the phase-changeable material pattern overlies the protrusion of the molding layer, and another portion of the phase-changeable material pattern extends through the protrusion. The electrically insulative material of the oxidation barrier may cover the phase-changeable material pattern and/or extend along and cover the entire area at which the protrusion of the molding layer and the portion of the phase-change material pattern disposed on the protrusion adjoin.
Abstract translation: 相变存储器件具有氧化阻挡层以防止存储器细胞污染或氧化。 在一个实施例中，半导体存储器件包括设置在半导体衬底上的成型层，相变材料图案和电绝缘材料的氧化屏障。 成型层在其上部具有突出部。 可相变材料图案的一部分覆盖模制层的突起，并且相变材料图案的另一部分延伸穿过突出部。 氧化屏障的电绝缘材料可以覆盖相变材料图案和/或延伸并且覆盖模制层的突起和设置在突起上的相变材料图案的部分邻接的整个区域。
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27.发明授权Resistive memory devices including selected reference memory cells operating responsive to read operations 有权电阻式存储器件包括响应于读取操作而工作的选择的参考存储器单元公开(公告)号：US08023311B2
公开(公告)日：2011-09-20
申请号：US12358936
申请日：2009-01-23
Applicant: Hyun-Jo Kim , Kyung-Tae Nam , In-Gyu Baek , Se-Chung Oh , Jang-Eun Lee , Jun-Ho Jeong
Inventor： Hyun-Jo Kim , Kyung-Tae Nam , In-Gyu Baek , Se-Chung Oh , Jang-Eun Lee , Jun-Ho Jeong
IPC: G11C11/00
CPC classification number: G11C7/062 , G11C7/067 , G11C7/14 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/0016 , G11C13/004 , G11C2013/0054 , G11C2213/32 , G11C2213/79
Abstract: A Resistance based Random Access Memory (ReRAM) can include a sense amplifier circuit that includes a first input coupled to a bit line of a reference cell in a first block of the ReRAM responsive to a read operation to a second block.
Abstract translation: 基于电阻的随机存取存储器（ReRAM）可以包括读出放大器电路，其响应于对第二块的读取操作，包括耦合到ReRAM的第一块中的参考单元的位线的第一输入。
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28.发明授权Memory devices including multi-bit memory cells having magnetic and resistive memory elements and related methods 失效存储器件包括具有磁性和电阻存储元件的多位存储单元和相关方法公开(公告)号：US07952914B2
公开(公告)日：2011-05-31
申请号：US11804327
申请日：2007-05-17
Applicant: In-Gyu Baek , Jang-Eun Lee , Se-Chung Oh , Kyung-Tae Nam , Jun-Ho Jeong
Inventor： In-Gyu Baek , Jang-Eun Lee , Se-Chung Oh , Kyung-Tae Nam , Jun-Ho Jeong
IPC: G11C11/00
CPC classification number: G11C11/15 , G11C11/005 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C11/5607 , G11C11/5678 , G11C13/00 , G11C13/0004 , G11C13/02 , H01L27/224 , H01L27/228 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/14 , H01L45/146 , H01L45/147 , Y10S977/754 , Y10S977/935
Abstract: An integrated circuit memory device may include an integrated circuit substrate, and a multi-bit memory cell on the integrated circuit substrate. The multi-bit memory cell may be configured to store a first bit of data by changing a first characteristic of the multi-bit memory cell and to store a second bit of data by changing a second characteristic of the multi-bit memory cell. Moreover, the first and second characteristics may be different. Related methods are also discussed.
Abstract translation: 集成电路存储器件可以包括集成电路衬底和集成电路衬底上的多位存储单元。 多位存储器单元可以被配置为通过改变多位存储单元的第一特性来存储第一位数据，并且通过改变多位存储单元的第二特性来存储第二位数据。 此外，第一和第二特征可以不同。 还讨论了相关方法。
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公开(公告)号：US07645619B2
公开(公告)日：2010-01-12
申请号：US12073098
申请日：2008-02-29
Applicant: Se-Chung Oh , Jang-Eun Lee , Jun-Soo Bae , Hyun-Jo Kim , Kyung-Tae Nam , Young-Ki Ha
Inventor： Se-Chung Oh , Jang-Eun Lee , Jun-Soo Bae , Hyun-Jo Kim , Kyung-Tae Nam , Young-Ki Ha
IPC: H01L21/00
CPC classification number: G11C11/16 , B82Y10/00 , B82Y25/00 , G11B5/3909 , H01L27/228 , H01L43/08 , H01L43/12 , Y10T29/49034 , Y10T29/49044
Abstract: Example embodiments of the present invention disclose a semiconductor memory device and a method of forming a memory device. A semiconductor memory device may include a digit line disposed on a substrate, an intermediate insulating layer covering the digit line, a magnetic tunnel junction (MTJ) pattern disposed on the intermediate insulating layer and over the digit line, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., and a bit line connected to the capping pattern and disposed to intersect the digit line. A method of forming a semiconductor memory device may include forming a digit line on a substrate, forming an intermediate insulating layer covering the digit line, forming a magnetic tunnel junction (MTJ) pattern on the intermediate insulating layer, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., performing an annealing operation at a temperature of about 350° C. or higher, and forming a bit line connected to the capping pattern and disposed to intersect the digit line.
Abstract translation: 本发明的示例性实施例公开了半导体存储器件和形成存储器件的方法。 半导体存储器件可以包括设置在衬底上的数字线，覆盖数字线的中间绝缘层，设置在中间绝缘层上方和数字线上的磁性隧道结（MTJ）图案，MTJ图案包括顺序堆叠 下磁性图案，上磁性图案和封盖图案，其中封盖图案在高于约280℃的温度下不与上磁性图案反应，而位线连接到封盖图案并且设置成与数字线相交 。 形成半导体存储器件的方法可以包括在衬底上形成数字线，形成覆盖数字线的中间绝缘层，在中间绝缘层上形成磁隧道结（MTJ）图案，MTJ图案包括顺序层叠的 较低的磁性图案，上部磁性图案和封盖图案，其中封盖图案在高于约280℃的温度下不与上部磁性图案反应，在约350℃或更高的温度下进行退火操作， 并且形成连接到所述封盖图案并且设置成与所述数字线相交的位线。
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公开(公告)号：US20090212273A1
公开(公告)日：2009-08-27
申请号：US12388707
申请日：2009-02-19
Applicant: Jin-Shi Zhao , Jang-Eun Lee , In-Gyu Baek , Hyun-Jun Sim , Xiang-Shu Li , Eun-Kyung Yim
Inventor： Jin-Shi Zhao , Jang-Eun Lee , In-Gyu Baek , Hyun-Jun Sim , Xiang-Shu Li , Eun-Kyung Yim
CPC classification number: G11C13/02 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2213/31 , G11C2213/32 , H01L27/101 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/146 , H01L45/147
Abstract: Provided is a semiconductor device including a resistive memory element. The semiconductor device includes a substrate and the resistive memory element disposed on the substrate. The resistive memory element has resistance states of a plurality of levels according to generation and dissipation of at least one platinum bridge therein.
Abstract translation: 提供了包括电阻式存储元件的半导体器件。 半导体器件包括衬底和设置在衬底上的电阻性存储元件。 根据其中至少一个铂桥的产生和耗散，电阻性存储元件具有多个电平的电阻状态。
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