公开(公告)号：US20100006919A1

公开(公告)日：2010-01-14

申请号：US12484339

申请日：2009-06-15

Applicant: Suk-pil KIM ,  Yoon-dong PARK ,  June-mo KOO ,  Tae-eung YOON

Inventor： Suk-pil KIM ,  Yoon-dong PARK ,  June-mo KOO ,  Tae-eung YOON

IPC: H01L27/115 ,  H01L29/788 ,  H01L21/8246

CPC classification number: H01L27/11556 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11578

Abstract: A nonvolatile memory device is provided that includes; a first semiconductor layer extending in a first direction, a second semiconductor layer extending in parallel with and separated from the first semiconductor layer, an isolation layer between the first semiconductor layer and second semiconductor layer, a first control gate electrode between the first semiconductor layer and the isolation layer, a second control gate electrode between the second semiconductor layer and the isolation layer, wherein the second control gate electrode and first control gate electrode are respectively disposed at opposite sides of the isolation layer, a first charge storing layer between the first control gate electrode and the first semiconductor layer, and a second charge storing layer between the second control gate electrode and the second semiconductor layer.

Abstract translation: 提供了一种非易失性存储装置，包括： 沿第一方向延伸的第一半导体层，与第一半导体层平行延伸并与第一半导体层分离的第二半导体层，在第一半导体层和第二半导体层之间的隔离层，第一半导体层与第一半导体层之间的第一半导体层， 所述隔离层，所述第二半导体层和所述隔离层之间的第二控制栅极电极，其中所述第二控制栅极电极和所述第一控制栅电极分别设置在所述隔离层的相对侧，所述第一控制栅极之间的第一电荷存储层 栅电极和第一半导体层，以及在第二控制栅电极和第二半导体层之间的第二电荷存储层。

公开(公告)号：US20090285027A1

公开(公告)日：2009-11-19

申请号：US12318651

申请日：2009-01-05

Applicant: Tae-hee Lee ,  Won-joo Kim ,  June-mo Koo ,  Tae-eung Yoon

Inventor： Tae-hee Lee ,  Won-joo Kim ,  June-mo Koo ,  Tae-eung Yoon

IPC: G11C16/04 ,  G11C16/06 ,  G11C7/00

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

Abstract: A non-volatile memory device, which includes a plurality of memory transistors that are coupled with a plurality of bit lines and a plurality of word lines, and methods of operating a non-volatile memory device are provided. A selected bit line for programming and unselected bit lines for preventing programming are determined from the plurality of bit lines. An inhibiting voltage is applied to at least one inhibiting word line chosen from the plurality of word lines. The at least one inhibiting word line includes a word line positioned closest to a string selection line. A programming voltage is applied to a selected word line chosen from the plurality of word lines. Data is programmed into a memory transistor coupled with the selected word line and the selected bit line while preventing data from being programming into memory transistors coupled with the unselected bit line.

Abstract translation: 提供了包括与多个位线和多个字线耦合的多个存储晶体管的非易失性存储器件以及操作非易失性存储器件的方法。 从多个位线确定用于编程的选择位线和用于防止编程的未选位线。 对从多个字线中选择的至少一个禁止字线施加抑制电压。 至少一个禁止字线包括最靠近字符串选择线定位的字线。 将编程电压施加到从多个字线中选择的选定字线。 数据被编程到与所选择的字线和所选择的位线耦合的存储晶体管中，同时防止数据被编程到与未选位线耦合的存储晶体管中。

公开(公告)号：US20090253255A1

公开(公告)日：2009-10-08

申请号：US12457366

申请日：2009-06-09

Applicant: Won-joo Kim ,  June-mo Koo ,  Seung-hwan Song ,  Suk-pil Kim ,  Yoon-dong Park ,  Jong-jin Lee

Inventor： Won-joo Kim ,  June-mo Koo ,  Seung-hwan Song ,  Suk-pil Kim ,  Yoon-dong Park ,  Jong-jin Lee

IPC: H01L21/28

CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792

Abstract: Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.

Abstract translation: 示例性实施例涉及半导体器件及其制造方法。 根据示例实施例的半导体器件可以在读取操作期间具有减小的干扰，并且减少短信道效应。 半导体器件可以包括具有主体和从主体突出的一对鳍片的半导体衬底。 可以在一对翅片的内侧壁的上部形成内隔离层绝缘层，以减少对一对翅片之间的区域的入口。 栅极电极可以覆盖一对鳍片的外部侧壁的一部分，并且可以跨越内部间隔物绝缘层延伸，以便在一对鳍片之间限定空隙。 栅绝缘层可以插入在栅电极和一对鳍之间。

公开(公告)号：US07585755B2

公开(公告)日：2009-09-08

申请号：US11978567

申请日：2007-10-30

Applicant: Seung-hwan Song ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Jae-woong Hyun ,  Choong-ho Lee ,  Tae-hun Kim

Inventor： Seung-hwan Song ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Jae-woong Hyun ,  Choong-ho Lee ,  Tae-hun Kim

IPC: H01L21/8239 ,  H01L29/788 ,  H01L29/792 ,  H01L27/105

CPC classification number: H01L21/84 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203

Abstract: A method of fabricating a non-volatile memory device according to example embodiments may include forming a semiconductor layer on a substrate. A plurality of lower charge storing layers may be formed on a bottom surface of the semiconductor layer. A plurality of lower control gate electrodes may be formed on the plurality of lower charge storing layers. A plurality of upper charge storing layers may be formed on a top surface of the semiconductor layer. A plurality of upper control gate electrodes may be formed on the plurality of upper charge storing layers, wherein the plurality of lower and upper control gate electrodes may be arranged alternately.

Abstract translation: 根据示例性实施例的制造非易失性存储器件的方法可包括在衬底上形成半导体层。 多个下电荷存储层可以形成在半导体层的底表面上。 可以在多个下电荷存储层上形成多个下控制栅电极。 多个上电荷存储层可以形成在半导体层的顶表面上。 多个上部控制栅极电极可以形成在多个上部电荷存储层上，其中多个下部和上部控制栅电极可以交替布置。

公开(公告)号：US07551491B2

公开(公告)日：2009-06-23

申请号：US11715404

申请日：2007-03-08

Applicant: Won-joo Kim ,  Suk-pil Kim ,  Jae-woong Hyun ,  Yoon-dong Park ,  June-mo Koo

Inventor： Won-joo Kim ,  Suk-pil Kim ,  Jae-woong Hyun ,  Yoon-dong Park ,  June-mo Koo

IPC: G11C11/34

CPC classification number: G11C16/0433 ,  G11C16/0491 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

Abstract: Unit cells of a non-volatile memory device and a method thereof are provided. In an example, the unit cell may include a first memory transistor and a second memory transistor connected to each other in series and further connected in common to a word line, the first and second memory transistors including first and second storage nodes, respectively, the first and second storage nodes configured to execute concurrent memory operations. In another example, the unit cell may include a semiconductor substrate in which first and second bit line regions are defined, first and second storage node layers respectively formed on the semiconductor substrate between the first and second bit line regions, a first pass gate electrode formed on the semiconductor substrate between the first bit line region and the first storage node layer, a second pass gate electrode formed on the semiconductor substrate between the second bit line region and the second storage node layer, a third pass gate electrode formed on the semiconductor substrate between the first and second storage node layers, a third bit line region formed in a portion of the semiconductor substrate under the third pass gate electrode and a control gate electrode extending across the first and second storage node layers. The example unit cells may be implemented within a non-volatile memory device (e.g., a flash memory device), such that the non-volatile memory device may include a plurality of example unit cells.

Abstract translation: 提供非易失性存储器件的单元电池及其方法。 在一个示例中，单元可以包括串联连接并进一步连接到字线的第一存储晶体管和第二存储晶体管，第一和第二存储晶体管分别包括第一和第二存储节点， 配置为执行并发存储器操作的第一和第二存储节点。 在另一示例中，单元可以包括其中限定了第一和第二位线区域的半导体衬底，分别形成在第一和第二位线区域之间的半导体衬底上的第一和第二存储节点层，形成的第一遍栅极电极 在第一位线区域和第一存储节点层之间的半导体衬底上，形成在第二位线区域和第二存储节点层之间的半导体衬底上的第二遍栅极电极，形成在半导体衬底上的第三栅极电极 在所述第一和第二存储节点层之间形成第三位线区域，所述第三位线区域形成在所述第三栅极电极下方的所述半导体衬底的一部分中，以及跨越所述第一和第二存储节点层延伸的控制栅电极。 示例性单元单元可以在非易失性存储器件（例如，闪存器件）内实现，使得非易失性存储器件可以包括多个示例单位单元。

公开(公告)号：US20080111199A1

公开(公告)日：2008-05-15

申请号：US11976004

申请日：2007-10-19

Applicant: Suk-pil KIM ,  Yoon-dong Park ,  Jong-Jin Lee ,  Won-joo Kim ,  June-mo Koo ,  Seung-hwan Song

Inventor： Suk-pil KIM ,  Yoon-dong Park ,  Jong-Jin Lee ,  Won-joo Kim ,  June-mo Koo ,  Seung-hwan Song

IPC: H01L29/76 ,  H01L21/336

CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792

Abstract: Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.

Abstract translation: 示例性实施例涉及半导体器件及其制造方法。 根据示例实施例的半导体器件可以在读取操作期间具有减小的干扰，并且减少短信道效应。 半导体器件可以包括具有主体和从主体突出的一对鳍片的半导体衬底。 可以在一对翅片的内侧壁的上部形成内隔离层绝缘层，以减少对一对翅片之间的区域的入口。 栅极电极可以覆盖一对鳍片的外部侧壁的一部分，并且可以跨越内部间隔物绝缘层延伸，以便在一对鳍片之间限定空隙。 栅绝缘层可以插入在栅电极和一对鳍之间。

公开(公告)号：US20070190240A1

公开(公告)日：2007-08-16

申请号：US11567926

申请日：2006-12-07

Applicant: Hyuk-soon CHOI ,  Hyo-sug LEE ,  June-mo KOO ,  Kwang-hee KIM

Inventor： Hyuk-soon CHOI ,  Hyo-sug LEE ,  June-mo KOO ,  Kwang-hee KIM

IPC: B05D5/12

CPC classification number: B05D3/0263 ,  B05D1/00 ,  B05D1/185 ,  B05D2401/32 ,  B22F1/0018 ,  B22F1/0062 ,  B22F2998/00 ,  B82Y10/00 ,  B82Y30/00 ,  Y10T428/24355 ,  Y10T428/24372 ,  Y10T428/24479 ,  Y10T428/2457 ,  Y10T428/2462 ,  B22F1/0022

Abstract: A method of forming a nano-particle array by convective assembly and a convective assembly apparatus for the same are provided. The method of forming nano-particle array comprises: coating a plurality of nano-particles by forming a coating layer; performing a first convective assembly by moving a first substrate facing, in parallel to and spaced apart from a second substrate at a desired distance such that a colloidal solution including the coated nano-particles is between the first and second substrate; and performing a second convective assembly for evaporating a solvent by locally heating a surface of the colloidal solution drawn when the first substrate is moved in parallel relative to the second substrate. The present invention provides the method of forming the nano-particle array where nano-particles having a particle size from a few to several tens of nanometers are uniformly arrayed on a large area substrate at a low cost, and the convective assembly apparatus for the same.

Abstract translation: 提供了通过对流组装形成纳米颗粒阵列的方法和用于其的对流组装装置。 形成纳米颗粒阵列的方法包括：通过形成涂层来涂覆多个纳米颗粒; 通过将第一衬底移动到与第二衬底平行并间隔开所需距离的方式执行第一对流组件，使得包含涂覆的纳米颗粒的胶体溶液位于第一和第二衬底之间; 以及执行用于蒸发溶剂的第二对流组件，其通过局部加热当所述第一衬底相对于所述第二衬底平行移动时所绘制的所述胶体溶液的表面而蒸发溶剂。 本发明提供了形成纳米粒子阵列的方法，其中纳米粒子具有几个到几十个纳米的粒子以低成本均匀地排列在大面积基底上，而对流装配装置 。

公开(公告)号：US20070065961A1

公开(公告)日：2007-03-22

申请号：US11505968

申请日：2006-08-18

Applicant: Sung-Ho Park ,  Bum-Seok Seo ,  Myoung-Jae Lee ,  June-Mo Koo ,  Sun-Ae Seo ,  Young-Kwan Cha

Inventor： Sung-Ho Park ,  Bum-Seok Seo ,  Myoung-Jae Lee ,  June-Mo Koo ,  Sun-Ae Seo ,  Young-Kwan Cha

IPC: H01L21/00

CPC classification number: H01L27/115 ,  C23C16/406 ,  C23C16/45553 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1616

Abstract: Example embodiments relate to a method of manufacturing amorphous NiO thin films and nonvolatile memory devices including amorphous thin films that use a resistance material. Other example embodiments relate to a method of manufacturing amorphous NiO thin films having improved switching and resistance characteristics by reducing a leakage current and non-volatile memory devices using an amorphous NiO thin film. Provided is a method of manufacturing an amorphous NiO thin film having improved switching behavior by reducing leakage current and improving resistance characteristics. The method may include preparing a substrate in a vacuum chamber, preparing a nickel precursor material, preparing a source gas by vaporizing the nickel precursor material, preparing a reaction gas, preparing a purge gas and forming a monolayer NiO thin film on the substrate by performing one cycle of sequentially supplying the source gas, the purge gas, the reaction gas and the purge gas into the vacuum chamber.

Abstract translation: 示例性实施例涉及制造非晶NiO薄膜的方法和包括使用电阻材料的非晶薄膜的非易失性存储器件。 其他示例实施例涉及通过减少漏电流而制造具有改进的开关和电阻特性的非晶NiO薄膜的方法，以及使用非晶态NiO薄膜的非易失性存储器件。 提供了通过减少漏电流和改善电阻特性来制造具有改进的开关行为的非晶NiO薄膜的方法。 该方法可以包括在真空室中准备衬底，制备镍前体材料，通过汽化镍前体材料制备源气体，制备反应气体，制备吹扫气体并通过执行在衬底上形成单层NiO薄膜 将源气体，净化气体，反应气体和吹扫气体依次供给到真空室中的一个循环。

公开(公告)号：US20060027847A1

公开(公告)日：2006-02-09

申请号：US11193415

申请日：2005-08-01

Applicant: June-mo Koo ,  Young-soo Park ,  Sang-min Shin ,  Suk-pil Kim

Inventor： June-mo Koo ,  Young-soo Park ,  Sang-min Shin ,  Suk-pil Kim

IPC: H01L29/00 ,  H01L21/00

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/65

Abstract: A ferroelectric capacitor comprises a first electrode comprising an alloy containing a first element and a second element of the periodic table of the elements, the first element being selected from the group consisting of Ir and Ru. A ferroelectric layer is disposed on the first electrode, wherein the ferroelectric layer comprises a ferroelectric material containing the second element. A second electrode is disposed on the ferroelectric layer. The ferroelectric capacitor can be provided as part of a memory cell of a ferroelectric memory.

公开(公告)号：US08120006B2

公开(公告)日：2012-02-21

申请号：US12585582

申请日：2009-09-18

Applicant: Suk-pil Kim ,  June-mo Koo ,  Tae-eung Yoon

Inventor： Suk-pil Kim ,  June-mo Koo ,  Tae-eung Yoon

IPC: H01L47/00 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L45/04 ,  H01L27/2409 ,  H01L27/249 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146

Abstract: Provided is a non-volatile memory device having a stacked structure that is easily highly integrated and a method of economically fabricating the non-volatile memory device. The non-volatile memory device may include at least one first electrode and at least one second electrode that cross each other. At least one data storage layer may be disposed on a section where the at least one first electrode and the at least one second electrode cross each other. The at least one first electrode may include a first conductive layer and a first semiconductor layer.

Abstract translation: 提供了具有容易高度集成的堆叠结构的非易失性存储器件以及经济地制造非易失性存储器件的方法。 非易失性存储器件可以包括至少一个第一电极和至少一个彼此交叉的第二电极。 至少一个数据存储层可以设置在至少一个第一电极和至少一个第二电极彼此交叉的部分上。 所述至少一个第一电极可以包括第一导电层和第一半导体层。