公开(公告)号：US06838363B2

公开(公告)日：2005-01-04

申请号：US10402585

申请日：2003-03-28

Applicant: Karsten Wieczorek ,  Thorsten Kammler ,  Manfred Horstmann

Inventor： Karsten Wieczorek ,  Thorsten Kammler ,  Manfred Horstmann

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/425

CPC classification number: H01L29/66507 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6653

Abstract: The introduction of a barrier diffusion material, such as nitrogen, into a silicon-containing conductive region, for example the drain and source regions and the gate electrode of a field effect transistor, allows the formation of nickel silicide, which is substantially thermally stable up to temperatures of 500° C. Thus, the device performance may significantly improve as the sheet resistance of nickel silicide is significantly less than that of nickel disilicide.

Abstract translation: 诸如氮的阻挡扩散材料引入含硅导电区域，例如场效应晶体管的漏极和源极区域和栅电极，允许形成基本上热稳定的硅化镍 到500℃的温度。因此，随着硅化镍的薄层电阻显着小于二硅化镍的薄膜电阻，器件性能可能显着提高。

公开(公告)号：US06806153B2

公开(公告)日：2004-10-19

申请号：US10462893

申请日：2003-06-17

Applicant: Karsten Wieczorek ,  Manfred Horstmann ,  Thomas Feudel

Inventor： Karsten Wieczorek ,  Manfred Horstmann ,  Thomas Feudel

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/2022 ,  H01L21/26506 ,  H01L21/26513

Abstract: The present invention allows the manufacturing of field effect transistors with reduced thermal budget. A first amorphized region and a second amorphized region are formed in a substrate adjacent to the gate electrode by implanting ions of a non-doping element, the presence of which does not significantly alter the conductive properties of the substrate. The formation of the amorphized regions may be performed before or after the formation of a source region, a drain region, an extended source region and an extended drain region. The substrate is annealed to achieve solid phase epitaxial regrowth of the amorphized regions and to activate dopants in the source region, the drain region, the extended source region and the extended drain region.

Abstract translation: 本发明允许制造具有降低的热预算的场效应晶体管。 第一非晶化区域和第二非晶区域通过注入非掺杂元素的离子形成在与栅电极相邻的衬底中，其不存在不会显着地改变衬底的导电性能。 非晶化区域的形成可以在形成源极区域，漏极区域，扩展源极区域和延伸的漏极区域之前或之后进行。 将衬底退火以实现非晶化​​区域的固相外延再生长并激活源极区域，漏极区域，扩展源极区域和延伸漏极区域中的掺杂剂。

公开(公告)号：US06798028B2

公开(公告)日：2004-09-28

申请号：US09847622

申请日：2001-05-02

Applicant: Manfred Horstmann ,  Rolf Stephan ,  Karsten Wieczorek ,  Stephan Kruegel

Inventor： Manfred Horstmann ,  Rolf Stephan ,  Karsten Wieczorek ,  Stephan Kruegel

IPC: H01L2976

CPC classification number: H01L21/28052 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4933

Abstract: A transistor formed on a substrate comprises a gate electrode having a lateral extension at the foot of the gate electrode that is less than the average lateral extension of the gate electrode. The increased cross-section of the gate electrode compared to the rectangular cross-sectional shape of a prior art device provides for a significantly reduced gate resistance while the effective gate length, i.e., the lateral extension of the gate electrode at its foot, may be scaled down to a size of 100 nm and beyond. Moreover, a method for forming the field effect transistor described above is disclosed.

Abstract translation: 形成在基板上的晶体管包括栅电极，栅电极在栅极的脚处具有小于栅电极的平均横向延伸的横向延伸。 与现有技术的器件的矩形横截面形状相比，栅电极的横截面增加提供了显着降低的栅极电阻，而有效栅极长度，即栅电极在其脚处的横向延伸可以是 缩小到100nm以上的尺寸。 此外，公开了一种用于形成上述场效应晶体管的方法。

公开(公告)号：US06436724B1

公开(公告)日：2002-08-20

申请号：US09808391

申请日：2001-03-14

Applicant: Karsten Wieczorek ,  Manfred Horstmann ,  Christian Krüger

Inventor： Karsten Wieczorek ,  Manfred Horstmann ,  Christian Krüger

IPC: H01L2166

CPC classification number: H01L22/12

Abstract: A method of monitoring the temperature of a rapid thermal annealing (RTA) process and a test wafer for use in this process are disclosed. The method includes the step of forming a distorted surface region in a crystalline semiconductor wafer and the mounting of the wafer in a process chamber for performing the RTA process in a reaction gas containing ambient. The distorted surface region of the semiconductor wafer enables higher diffusion rates of reaction gas components into the wafer surface and therefore a higher growth rate of a reaction product film. The increase of the reaction product film thickness enables an increase of the film thickness measurement accuracy and thus the accuracy in determining the RTA temperature homogeneity. In one embodiment, a distorted surface region in a crystalline silicon test wafer is produced by implanting ions at low doses into a wafer substrate up to a pre-amorphization level of the surface crystalline lattice. As a low dose of heavy ions is sufficient for producing the distorted surface region, the test wafers are produced at low costs. Additionally, a method of reworking test wafers that have been used in an RTA monitoring method is presented. By reworking the test wafers and preparing for the next RTA-monitoring the wafer costs can be efficiently reduced.

Abstract translation: 公开了一种监测快速热退火（RTA）工艺的温度和用于该工艺的测试晶片的方法。 该方法包括在晶体半导体晶片中形成失真的表面区域以及将晶片安装在用于在含有环境的反应气体中进行RTA处理的处理室中的步骤。 半导体晶片的变形的表面区域能够使反应气体成分进入晶片表面的扩散速率更高，因此反应产物膜的生长速度更高。 反应产物膜厚度的增加能够提高膜厚测量精度，从而能够提高测定RTA温度均匀性的精度。 在一个实施例中，晶体硅测试晶片中的失真的表面区域是通过将低剂量的离子注入到晶片衬底中而产生的，直到表面晶格的非晶化阶段为止。 由于低剂量的重离子足以产生变形的表面区域，所以以低成本生产测试晶片。 另外，提出了一种在RTA监控方法中使用的重做测试晶片的方法。 通过重新测试晶片并准备下一个RTA监控，可以有效降低晶圆成本。

公开(公告)号：US06410410B1

公开(公告)日：2002-06-25

申请号：US09852535

申请日：2001-05-10

Applicant: Thomas Feudel ,  Manfred Horstmann ,  Karsten Wieczorek

Inventor： Thomas Feudel ,  Manfred Horstmann ,  Karsten Wieczorek

IPC: H01L21225

CPC classification number: H01L29/6659 ,  H01L21/2255 ,  H01L29/42368 ,  H01L29/7833

Abstract: A method is disclosed in which a lightly doped region in a semiconductor layer is obtained by diffusing dopant atoms of a first and second type into the underlying semiconductor layer. Preferably, the method is applied to the formation of lightly doped source and drain regions in a field effect transistor so as to obtain a required gradual dopant concentration transition from the general region to the drain and source regions for avoiding the hot carrier effect. Advantageously, a diffusion of the dopant atoms is initiated during an oxidizing step in which the thickness of the gate insulation layer is increased at the edge portions thereof.

Abstract translation: 公开了一种通过将第一和第二类型的掺杂剂原子扩散到下面的半导体层中而获得半导体层中的轻掺杂区域的方法。 优选地，该方法被应用于在场效应晶体管中形成轻掺杂的源极和漏极区域，以便获得从一般区域到漏极和源极区域所需的逐渐掺杂剂浓度跃迁，以避免热载流子效应。 有利地，掺杂剂原子的扩散在其栅极绝缘层的厚度在其边缘部分增加的氧化步骤期间开始。

公开(公告)号：US08440516B2

公开(公告)日：2013-05-14

申请号：US12752487

申请日：2010-04-01

Applicant: Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

Inventor： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

IPC: H01L21/8234

CPC classification number: H01L29/66621 ,  H01L29/165 ,  H01L29/66583 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method of forming a field effect transistor comprises providing a substrate comprising a biaxially strained layer of a semiconductor material. A gate electrode is formed on the biaxially strained layer of semiconductor material. A raised source region and a raised drain region are formed adjacent the gate electrode. Ions of a dopant material are implanted into the raised source region and the raised drain region to form an extended source region and an extended drain region. Moreover, in methods of forming a field effect transistor according to embodiments of the present invention, a gate electrode can be formed in a recess of a layer of semiconductor material. Thus, a field effect transistor wherein a source side channel contact region and a drain side channel contact region located adjacent a channel region are subject to biaxial strain can be obtained.

Abstract translation: 形成场效应晶体管的方法包括提供包括半导体材料的双轴应变层的衬底。 在半导体材料的双轴应变层上形成栅电极。 在栅电极附近形成凸起的源区和升高的漏极区。 将掺杂剂材料的离子注入到凸起的源极区域和隆起的漏极区域中，以形成扩展的源极区域和延伸的漏极区域。 此外，在形成根据本发明的实施例的场效应晶体管的方法中，可以在半导体材料层的凹部中形成栅电极。 因此，可以获得其中位于沟道区附近的源极侧沟道接触区域和漏极侧沟道接触区域受到双轴应变的场效应晶体管。

公开(公告)号：US20120161240A1

公开(公告)日：2012-06-28

申请号：US13337690

申请日：2011-12-27

Applicant: Stephan Kronholz ,  Juergen Amon ,  Manfred Horstmann

Inventor： Stephan Kronholz ,  Juergen Amon ,  Manfred Horstmann

IPC: H01L27/088 ,  H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  Y02P80/30

Abstract: When incorporating a strain-inducing semiconductor alloy in one type of sophisticated transistors, the removal of sacrificial cap materials, such as a spacer layer, sacrificial spacer elements and dielectric cap materials, may be accomplished by using, at least in a first phase of the removal process, an efficient etch stop liner material, which may thus reduce the material loss in the drain and source extension regions that are formed prior to the deposition of the strain-inducing semiconductor material. Moreover, the drain and source extension regions of the other type of transistor may be formed with superior process uniformity due to a reduced material erosion of the corresponding spacer elements.

Abstract translation: 当在一种类型的复杂晶体管中引入应变诱导半导体合金时，可以通过使用至少在第一阶段中的至少第一阶段来完成除去牺牲帽材料，例如间隔层，牺牲隔离元件和电介质盖材料 去除工艺，有效的蚀刻停止衬垫材料，其可以因此减少在应变诱导半导体材料的沉积之前形成的漏极和源极延伸区域中的材料损耗。 此外，由于相应的间隔元件的材料侵蚀减少，另一种类型的晶体管的漏极和源极延伸区域可以形成为具有优异的工艺均匀性。

公开(公告)号：US20110104878A1

公开(公告)日：2011-05-05

申请号：US13005676

申请日：2011-01-13

Applicant: Sven Beyer ,  Manfred Horstmann ,  Patrick Press ,  Wolfgang Buchholtz

Inventor： Sven Beyer ,  Manfred Horstmann ,  Patrick Press ,  Wolfgang Buchholtz

IPC: H01L21/20

CPC classification number: H01L21/823807 ,  H01L29/165 ,  H01L29/66621 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/7849

Abstract: By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced.

Abstract translation: 通过在一个有源区中形成基本上连续且均匀的半导体合金，同时在第二有源区中图案化半导体合金，以便在其中心部分提供基极半导体材料，可以诱发不同类型的应变， 可以使用基底半导体材料的相应的覆盖层，用于形成栅极电介质的完善的工艺技术。 在一些示例性实施例中，提供了基本上自对准的工艺，其中栅电极可以基于层形成，其也已经用于限定一个有源区的基极半导体材料的中心部分。 因此，通过使用单个半导体合金，可以单独提高不同导电类型的晶体管的性能。

公开(公告)号：US07906383B2

公开(公告)日：2011-03-15

申请号：US12045095

申请日：2008-03-10

Applicant: Ralf Richter ,  Andy Wei ,  Manfred Horstmann ,  Joerg Hohage

Inventor： Ralf Richter ,  Andy Wei ,  Manfred Horstmann ,  Joerg Hohage

IPC: H01L21/8238 ,  H01L21/311 ,  H01L21/70 ,  H01L27/085

CPC classification number: H01L21/823807 ,  H01L21/823412 ,  H01L21/823425 ,  H01L29/7843

Abstract: By forming a stressed dielectric layer on different transistors and subsequently relaxing a portion thereof, the overall process efficiency in an approach for creating strain in channel regions of transistors by stressed overlayers may be enhanced while nevertheless transistor performance gain may be obtained for each type of transistor, since a highly stressed material positioned above the previously relaxed portion may also efficiently affect the underlying transistor.

Abstract translation: 通过在不同的晶体管上形成应力介电层并随后放松其一部分，可以增强用于通过应力覆盖层在晶体管的沟道区域中产生应变的方法中的整体工艺效率，同时可以为每种类型的晶体管获得晶体管性能增益 由于位于先前松弛部分之上的高应力材料也可有效地影响底层晶体管。

公开(公告)号：US07696052B2

公开(公告)日：2010-04-13

申请号：US11558006

申请日：2006-11-09

Applicant: Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann ,  Peter Javorka ,  Joe Bloomquist

Inventor： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann ,  Peter Javorka ,  Joe Bloomquist

IPC: H01L21/336

CPC classification number: H01L29/66628 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66787 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78621 ,  H01L29/78684

Abstract: By recessing drain and source regions, a highly stressed layer, such as a contact etch stop layer, may be formed in the recess in order to enhance the strain generation in the adjacent channel region of a field effect transistor. Moreover, a strained semiconductor material may be positioned in close proximity to the channel region by reducing or avoiding undue relaxation effects of metal silicides, thereby also providing enhanced efficiency for the strain generation. In some aspects, both effects may be combined to obtain an even more efficient strain-inducing mechanism.

Abstract translation: 通过凹陷漏极和源极区域，可以在凹部中形成诸如接触蚀刻停止层的高应力层，以增强场效应晶体管的相邻沟道区域中的应变产生。 此外，应变半导体材料可以通过减少或避免金属硅化物的不适当的松弛效应来定位在靠近沟道区域，从而也为应变产生提供增强的效率。 在一些方面，两种效应可以组合以获得更有效的应变诱导机制。