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    Spacer patterned augmentation of tri-gate transistor gate length
    26.
    发明申请
    Spacer patterned augmentation of tri-gate transistor gate length 有权
    三栅极晶体管栅极长度的间隔图案化扩充

    公开(公告)号：US20090168498A1

    公开(公告)日：2009-07-02

    申请号：US12006063

    申请日：2007-12-28

    Applicant: Ravi Pillarisetty ,  Suman Datta ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah

    Inventor： Ravi Pillarisetty ,  Suman Datta ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah

    IPC: G11C11/40 ,  H01L21/283

    CPC classification number: H01L27/1104 ,  H01L27/0207

    Abstract: In general, in one aspect, a method includes forming a semiconductor substrate having N-diffusion and P-diffusion regions. A gate stack is formed over the semiconductor substrate. A gate electrode hard mask is formed over the gate stack. The gate electrode hard mask is augmented around pass gate transistors with a spacer material. The gate stack is etched using the augmented gate electrode hard mask to form the gate electrodes. The gate electrodes around the pass gate have a greater length than other gate electrodes.

    Abstract translation: 通常，一方面，一种方法包括形成具有N-扩散和P-扩散区域的半导体衬底。 在半导体衬底上形成栅叠层。 栅电极硬掩模形成在栅叠层上。 栅极电极硬掩模用隔离材料增加在通过栅极晶体管周围。 使用增强的栅极电极硬掩模蚀刻栅极堆叠以形成栅电极。 通过栅极周围的栅电极具有比其它栅电极更大的长度。

    METHOD TO INTRODUCE UNIAXIAL STRAIN IN MULTIGATE NANOSCALE TRANSISTORS BY SELF ALIGNED SI TO SIGE CONVERSION PROCESSES AND STRUCTURES FORMED THEREBY
    28.
    发明申请
    METHOD TO INTRODUCE UNIAXIAL STRAIN IN MULTIGATE NANOSCALE TRANSISTORS BY SELF ALIGNED SI TO SIGE CONVERSION PROCESSES AND STRUCTURES FORMED THEREBY 有权
    通过自对准SI引入多元纳米晶体管中的单轴应变的方法来标识形成的转换过程和结构

    公开(公告)号：US20090085062A1

    公开(公告)日：2009-04-02

    申请号：US11864726

    申请日：2007-09-28

    Applicant: Been-Yih Jin ,  Brian Doyle ,  Jack Kavalieros ,  Suman Datta

    Inventor： Been-Yih Jin ,  Brian Doyle ,  Jack Kavalieros ,  Suman Datta

    IPC: H01L29/778 ,  H01L21/336

    CPC classification number: H01L29/7851 ,  H01L29/66795 ,  H01L29/7848

    Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods may include providing a gate electrode comprising a top surface and first and second laterally opposite sidewalls, wherein a hard mask is disposed on the top surface, a source drain region disposed on opposite sides of the gate electrode, and a spacer disposed on the first and second laterally opposed sidewalls of the gate electrode, forming a silicon germanium layer on exposed portions of the top surface and the first and second laterally opposite sidewalls of the source drain region and then oxidizing a portion of the silicon germanium layer, wherein a germanium portion of the silicon germanium layer is forced down into the source drain region to convert a silicon portion of the source drain region into a silicon germanium portion of the source drain region.

    Abstract translation: 描述形成微电子结构的方法。 这些方法的实施例可以包括提供包括顶表面和第一和第二横向相对的侧壁的栅电极，其中硬掩模设置在顶表面上，源极漏极区域设置在栅电极的相对侧上， 在栅电极的第一和第二横向相对的侧壁上，在源漏区的顶表面和第一和第二横向相对的侧壁的暴露部分上形成硅锗层，然后氧化硅锗层的一部分，其中 硅锗层的锗部分被迫下降到源极漏极区域中，以将源极区域的硅部分转换成源极漏极区域的硅锗部分。

    NONPLANAR SEMICONDUCTOR DEVICE WITH PARTIALLY OR FULLY WRAPPED AROUND GATE ELECTRODE AND METHODS OF FABRICATION
    30.
    发明申请
    NONPLANAR SEMICONDUCTOR DEVICE WITH PARTIALLY OR FULLY WRAPPED AROUND GATE ELECTRODE AND METHODS OF FABRICATION 有权
    非门式半导体器件，部分或完全包裹在门电极和制造方法

    公开(公告)号：US20090061572A1

    公开(公告)日：2009-03-05

    申请号：US12259464

    申请日：2008-10-28

    Applicant: Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

    Inventor： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

    IPC: H01L21/336

    CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/66795

    Abstract: A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

    Abstract translation: 描述了非平面半导体器件及其制造方法。 非平面半导体器件包括半导体本体，该半导体本体具有与形成在绝缘基板上方的底表面相对的顶表面，其中半导体本体具有一对横向相对的侧壁。 在半导体本体的横向相对的侧壁和半导体本体的底表面的至少一部分上的半导体本体的顶表面上形成栅极电介质。 栅极电极形成在半导体本体的顶表面上并与半导体本体的横向相对的侧壁上的栅电介质相邻并位于半导体本体的底表面上的栅电介质之下的栅电介质上。 在栅电极的相对侧的半导体本体中形成一对源/漏区。

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