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    MEMORY SYSTEMS AND METHODS OF INITIALLIZING THE SAME
    25.
    发明申请
    MEMORY SYSTEMS AND METHODS OF INITIALLIZING THE SAME 有权
    记忆系统及其初始化方法

    公开(公告)号：US20120179871A1

    公开(公告)日：2012-07-12

    申请号：US13421964

    申请日：2012-03-16

    Applicant: Jin-Hyeok CHOI ,  Sung-Hoon LEE ,  Si-Hoon HONG ,  Tae-Keun JEON

    Inventor： Jin-Hyeok CHOI ,  Sung-Hoon LEE ,  Si-Hoon HONG ,  Tae-Keun JEON

    IPC: G06F12/00

    CPC classification number: G06F12/0646

    Abstract: A memory system is provided includes a host processor, and a plurality of cascade connected memory cards connected to the host processor. Each of the memory cards stores a same default relative card address (RCA) prior to initialization of the memory system. The host processor is configured to sequentially access each memory card using the default RCA, and to change the default RCA to a unique RCA upon each sequential access.

    Abstract translation: 提供了一种存储器系统，包括主处理器和连接到主处理器的多个级联连接的存储卡。 每个存储卡在存储器系统的初始化之前存储相同的默认相对卡地址（RCA）。 主处理器配置为使用默认RCA顺序访问每个存储卡，并且在每次顺序访问时将默认RCA更改为唯一的RCA。

    Semiconductor memory devices performing erase operation using erase gate and methods of manufacturing the same
    26.
    发明授权
    Semiconductor memory devices performing erase operation using erase gate and methods of manufacturing the same 失效
    使用擦除栅极进行擦除操作的半导体存储器件及其制造方法

    公开(公告)号：US08119480B2

    公开(公告)日：2012-02-21

    申请号：US12923593

    申请日：2010-09-29

    Applicant: Sung-Hoon Lee ,  Sungil Park ,  Young-Gu Jin ,  Jongseob Kim ,  Ki-Ha Hong

    Inventor： Sung-Hoon Lee ,  Sungil Park ,  Young-Gu Jin ,  Jongseob Kim ,  Ki-Ha Hong

    IPC: H01L21/336

    CPC classification number: H01L29/792 ,  G11C16/10 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/66833

    Abstract: A semiconductor memory device performing an erase operation using an erase gate and a method of manufacturing the same are provided. The memory device may include a charge trap layer storing a first charge transfer medium having a first polarity and at least one erase gate. The at least one erase gate may be formed below the charge trap layer. A second charge transfer medium, which has a second polarity opposite to the first polarity, may be stored in the at least one erase gate. During the erase operation, the second charge transfer medium migrates to the charge trap layer causing the first charge transfer medium to combine with the second charge transfer medium.

    Abstract translation: 提供了使用擦除栅极执行擦除操作的半导体存储器件及其制造方法。 存储器件可以包括存储具有第一极性的第一电荷转移介质和至少一个擦除栅极的电荷陷阱层。 至少一个擦除栅极可以形成在电荷陷阱层下面。 具有与第一极性相反的第二极性的第二电荷转移介质可以存储在至少一个擦除栅中。 在擦除操作期间，第二电荷转移介质迁移到电荷捕获层，使得第一电荷转移介质与第二电荷转移介质组合。

    Semiconductor memory devices performing erase operation using erase gate and methods of manufacturing the same
    30.
    发明申请
    Semiconductor memory devices performing erase operation using erase gate and methods of manufacturing the same 失效
    使用擦除栅极进行擦除操作的半导体存储器件及其制造方法

    公开(公告)号：US20110021014A1

    公开(公告)日：2011-01-27

    申请号：US12923593

    申请日：2010-09-29

    Applicant: Sung-Hoon Lee ,  Sungil Park ,  Young-Gu Jin ,  Jongseob Kim ,  Ki-Ha Hong

    Inventor： Sung-Hoon Lee ,  Sungil Park ,  Young-Gu Jin ,  Jongseob Kim ,  Ki-Ha Hong

    IPC: H01L21/336

    CPC classification number: H01L29/792 ,  G11C16/10 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/66833

    Abstract: A semiconductor memory device performing an erase operation using an erase gate and a method of manufacturing the same are provided. The memory device may include a charge trap layer storing a first charge transfer medium having a first polarity and at least one erase gate. The at least one erase gate may be formed below the charge trap layer. A second charge transfer medium, which has a second polarity opposite to the first polarity, may be stored in the at least one erase gate. During the erase operation, the second charge transfer medium migrates to the charge trap layer causing the first charge transfer medium to combine with the second charge transfer medium.

    Abstract translation: 提供了使用擦除栅极执行擦除操作的半导体存储器件及其制造方法。 存储器件可以包括存储具有第一极性的第一电荷转移介质和至少一个擦除栅极的电荷陷阱层。 至少一个擦除栅极可以形成在电荷陷阱层下面。 具有与第一极性相反的第二极性的第二电荷转移介质可以存储在至少一个擦除栅中。 在擦除操作期间，第二电荷转移介质迁移到电荷捕获层，使得第一电荷转移介质与第二电荷转移介质组合。

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