公开(公告)号：US20090158230A1

公开(公告)日：2009-06-18

申请号：US11955653

申请日：2007-12-13

Applicant: Henry A. Bonges, III ,  Terence B. Hook ,  William F. Pokorny ,  Jeffrey S. Zimmerman

Inventor： Henry A. Bonges, III ,  Terence B. Hook ,  William F. Pokorny ,  Jeffrey S. Zimmerman

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: A method is disclosed of determining allowable antenna limits for semiconductor-on-insulator (SOI) technology. In one embodiment, the method may include: determining antenna area on a gate; determining antenna area on a source/drain; determining a total gate insulator area between gate and source/drain nets; and calculating allowable antenna area as a function of the total gate insulator area between the nets such that a larger total antenna area is allowed for larger total gate insulator area between the nets.

Abstract translation: 公开了一种确定绝缘体上半导体（SOI）技术的允许天线极限的方法。 在一个实施例中，该方法可以包括：确定门上的天线面积; 确定源/漏极上的天线面积; 确定栅极和源极/漏极网之间的总栅极绝缘体面积; 并且计算作为网之间的总门绝缘体面积的函数的可允许天线面积，使得允许较大的总天线面积用于网之间较大的总栅极绝缘体面积。

公开(公告)号：US20090094567A1

公开(公告)日：2009-04-09

申请号：US11869176

申请日：2007-10-09

Applicant: Chung-Ping Eng ,  Terence B. Hook ,  Jeffrey S. Zimmerman

Inventor： Chung-Ping Eng ,  Terence B. Hook ,  Jeffrey S. Zimmerman

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  H01L23/60 ,  H01L2223/6677 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

Abstract: Method embodiments herein determine a connection order in which connections will be made to connect active devices to antennas within a given circuit design. The method also evaluates the possibilities that these connections to the antennas will cause charging damage in the devices that are connected to the antennas. Such possibilities are based on the connection order, the size of the antennas, and the likelihood that charges will flow from the antennas through insulators of the devices. If a significant possibility for damage exists, the method can reduce the size of the antenna.

Abstract translation: 本文的方法实施例确定连接顺序，其中将连接有源器件连接到给定电路设计内的天线。 该方法还评估了这些与天线的连接在连接到天线的设备中将导致充电损坏的可能性。 这种可能性基于连接顺序，天线的尺寸以及电荷将从天线通过设备的绝缘体流过的可能性。 如果存在损坏的重大可能性，则该方法可以减小天线的尺寸。

公开(公告)号：US07492016B2

公开(公告)日：2009-02-17

申请号：US11308513

申请日：2006-03-31

Applicant: Terence B. Hook ,  Anda C. Mocuta ,  Jeffrey W. Sleight ,  Anthony K. Stamper

Inventor： Terence B. Hook ,  Anda C. Mocuta ,  Jeffrey W. Sleight ,  Anthony K. Stamper

IPC: H01L23/62

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207

Abstract: A chip includes a CMOS structure having a bulk device disposed in a first region of a semiconductor substrate in conductive communication with an underlying bulk region of the substrate, the first region and the bulk region having a first crystal orientation. A SOI device is disposed in a semiconductor-on-insulator (“SOI”) layer separated from the bulk region of the substrate by a buried dielectric layer, the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor (“PFET”) and the SOI device includes an n-type field effect transistor (“NFET”) device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor in conductive communication with a gate conductor of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. The diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a diode's breakdown voltage.

Abstract translation: 芯片包括CMOS结构，其具有设置在半导体衬底的与衬底的下面的主体区域导电连通的第一区域中的本体器件，第一区域和主体区域具有第一晶体取向。 SOI器件设置在绝缘体上半导体（“SOI”）层中，该绝缘体绝缘体（“SOI”）层通过掩埋电介质层与衬底的主体区域分离，SOI层具有与第一晶体取向不同的晶体取向。 在一个示例中，体器件包括p型场效应晶体管（“PFET”），并且SOI器件包括n型场效应晶体管（“NFET”）器件。 或者，体器件可以包括NFET，并且SOI器件可以包括PFET。 当SOI器件具有与本体器件的栅极导体导通的栅极导体时，除了存在与体区域反向偏置导电连通的二极管之外，SOI器件可能发生充电损坏。 当栅极导体上的电压或SOI器件的源极或漏极区域上的电压超过二极管的击穿电压时，二极管可操作以将放电电流传导到体区。

公开(公告)号：US07310036B2

公开(公告)日：2007-12-18

申请号：US10905546

申请日：2005-01-10

Applicant: Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Terence B. Hook ,  Robert M. Rassel ,  Edmund J. Sprogis ,  Anthony K Stamper ,  William J. Murphy

Inventor： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Terence B. Hook ,  Robert M. Rassel ,  Edmund J. Sprogis ,  Anthony K Stamper ,  William J. Murphy

IPC: H01C1/08

CPC classification number: H01C7/1013 ,  H01C1/084 ,  H01L2924/0002 ,  Y10T29/49083 ,  Y10T29/49085 ,  Y10T29/49099 ,  Y10T29/49144 ,  Y10T29/49147 ,  H01L2924/00

Abstract: A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.

Abstract translation: 提供带散热片的电阻。 散热器包括具有导热性高的金属或其它热导体的导电路径。 为了避免使用热导体将电阻器短路接地，在热导体和电阻体之间插入有一层薄导电电绝缘体。 因此，电阻器可承载大量的电流，因为高导电性热导体将热量从电阻器传导到散热器。 除了降低寄生电容和其他寄生电效应之外，提供各种配置的导热体和散热片，提供良好的导热性能，这将降低电阻器的高频响应。

公开(公告)号：US06333204B1

公开(公告)日：2001-12-25

申请号：US09234809

申请日：1999-01-21

Applicant: Terence B. Hook ,  Hon-Sum P. Wong

Inventor： Terence B. Hook ,  Hon-Sum P. Wong

IPC: H01L2100

CPC classification number: H01L27/14609 ,  H01L27/14643 ,  H01L27/14683 ,  H01L27/14687

Abstract: The present invention is a dual epi active pixel sensor cell having a p− region of dual thickness and a method of making the same. The dual epi active pixel sensor cell produces a sensor with improved noise and latch-up reduction and improved red absorption. The thin p− epi region is positioned in the logic region for improved latch-up immunity. The thick p− epi is position in the pixel region for improved red absorption.

Abstract translation: 本发明是具有双重厚度的p-区的双外延有源像素传感器单元及其制造方法。 双外延有源像素传感器单元产生具有改善的噪声和闭锁减小和改善的红色吸收的传感器。 薄的p-外延区域位于逻辑区域中，以提高闭锁抗扰度。 厚p-epi位于像素区域以改善红色吸收。

公开(公告)号：US06278102B1

公开(公告)日：2001-08-21

申请号：US09415642

申请日：1999-10-12

Applicant: Terence B. Hook ,  Jeffrey B. Johnson ,  Robert Leidy ,  Hon-Sum P. Wong

Inventor： Terence B. Hook ,  Jeffrey B. Johnson ,  Robert Leidy ,  Hon-Sum P. Wong

IPC: H01L2700

CPC classification number: H01L27/14609 ,  H01L27/14603

Abstract: A method of detecting electromagnetic radiation with an active pixel sensor photosensitive device having an extremely thin virtual pinning layer formed by inverting semiconductor material at the surface of a photosensitive region. The thin pinning layer improves blue light response. The inverted pinning layer is produced by connecting a negative potential source to a transparent conductive layer, preferably made of indium-tin-oxide positioned over most of the photosensitive region. The conductive layer is insulated from the photosensitive region by a thin insulating layer. Connection to the pinning layer is through a coupling region formed in an area not covered by the conductive and insulating layers. Red light response is improved and the depth of the photosensitive region reduced by creating a strained layer, preferably of germanium silicon, deep within the photosensitive region. The strained layer has a modified bandgap which increases the absorption rate of red light.

Abstract translation: 一种用有源像素传感器感光装置检测电磁辐射的方法，该感光装置具有通过使感光区域的表面处的半导体材料反相而形成的极薄的虚拟钉扎层。 薄钉扎层改善了蓝光响应。 反向钉扎层是通过将负电位源连接到透明导电层而制成的，该透明导电层优选由位于感光区域的大部分上的氧化铟锡制成。 导电层通过薄的绝缘层与感光区域绝缘。 与钉扎层的连接通过形成在未被导电层和绝缘层覆盖的区域中的耦合区域。 通过在感光区域内形成深层的应变层，优选锗硅，可以改善红光响应并降低感光区的深度。 应变层具有改进的带隙，其增加红光的吸收率。

公开(公告)号：US6083794A

公开(公告)日：2000-07-04

申请号：US889991

申请日：1997-07-10

Applicant: Terence B. Hook ,  Dennis Hoyniak ,  Edward J. Nowak

Inventor： Terence B. Hook ,  Dennis Hoyniak ,  Edward J. Nowak

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/66659 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/7835 ,  H01L29/6659

Abstract: A method of producing an asymmetrical semiconductor device with ion implantation techniques and semiconductor devices constructed according to this method in which a barrier of ion absorbing material of height h is positioned beside a structure on a semiconductor surface. The barrier is located at a maximum distance d from one side of the structure, and an angled ion implant is directed at the side of the structure. The maximum distance d of the barrier from the side of the structure is equal to the height of the barrier h divided by the tangent of the angle of the ion implant so that the side of the structure is shadowed from the ion implant. A second ion implant is directed to the opposite side of the structure on the semiconductor surface, thereby forming a desired implant and producing the asymmetrical semiconductor device.

Abstract translation: 使用离子注入技术制造不对称半导体器件的方法和根据该方法构造的半导体器件，其中高度为h的离子吸收材料的势垒位于半导体表面上的结构旁边。 屏障位于结构一侧的最大距离d处，并且成角度的离子注入物指向结构侧。 阻挡层从结构侧面的最大距离d等于隔离层h的高度除以离子注入角度的切线，使得结构的一侧被离子注入物遮蔽。 第二离子注入被引导到半导体表面上的结构的相对侧，从而形成期望的注入并产生非对称半导体器件。

公开(公告)号：US5982225A

公开(公告)日：1999-11-09

申请号：US907149

申请日：1997-08-06

Applicant: Timothy E. Forhan ,  Terence B. Hook ,  Steven W. Mittl ,  Edward J. Nowak ,  Madhu Sayala ,  Ronald A. Warren

Inventor： Timothy E. Forhan ,  Terence B. Hook ,  Steven W. Mittl ,  Edward J. Nowak ,  Madhu Sayala ,  Ronald A. Warren

IPC: H03K17/10 ,  H03K17/14 ,  H03K17/06 ,  H03K17/687

CPC classification number: H03K17/102 ,  H03K17/145

Abstract: A circuit actively monitors and measures the amount of MOS device degradation due to, for example, the hot electron effect, and makes compensatory adjustments to device voltage levels or clock speed to maintain desired levels of functionality and performance. Monitoring can be done separately for NFET and PFET devices to selectively adjust for different degradation rates between the two. In operation, the monitor circuit compares the performance of a stressed device to a reference device, that is, an unstressed device which has not been degraded by the hot-electron effect. The monitor circuit outputs a signal indicating the amount of device degradation. This signal is used to adjust the supply voltage to that device or to the chip or otherwise compensate for the degradation. The monitor circuit can be formed on-chip or off-chip.

Abstract translation: 电路主动监测和测量由于例如热电子效应引起的MOS器件退化的量，并且对器件电压电平或时钟速度进行补偿性调整以维持期望的功能和性能水平。 可以分别对NFET和PFET器件进行监控，以选择性地调整两者之间的不同降解率。 在操作中，监视电路将应力装置的性能与参考装置进行比较，即，未受热电子效应劣化的未受应力的装置。 监视电路输出指示设备劣化量的信号。 该信号用于调整该器件或芯片的电源电压或以其他方式补偿降级。 监控电路可以片上或片外形成。

公开(公告)号：US5898196A

公开(公告)日：1999-04-27

申请号：US948739

申请日：1997-10-10

Applicant: Terence B. Hook ,  Hon-Sum P. Wong

Inventor： Terence B. Hook ,  Hon-Sum P. Wong

IPC: H01L27/144 ,  H01L27/146 ,  H01L31/062 ,  H01L29/76 ,  H01L31/113

CPC classification number: H01L27/14609 ,  H01L27/14643 ,  H01L27/14683 ,  H01L27/14687

Abstract: The present invention is a dual epi active pixel sensor cell having a p- region of dual thickness and a method of making the same. The dual epi active pixel sensor cell produces a sensor with improved noise and latch-up reduction and improved red absorption. The thin p- epi region is positioned in the logic region for improved latch-up immunity. The thick p- epi is positioned in the pixel region for improved red absorption.

Abstract translation: 本发明是具有双重厚度的p-区的双外延有源像素传感器单元及其制造方法。 双外延有源像素传感器单元产生具有改善的噪声和闭锁减小和改善的红色吸收的传感器。 薄的p-外延区域位于逻辑区域中，以提高闭锁抗扰度。 厚p-epi位于像素区域中以改善红色吸收。

公开(公告)号：US08994085B2

公开(公告)日：2015-03-31

申请号：US13551714

申请日：2012-07-18

Applicant: Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tenko Yamashita ,  Chun-Chen Yeh

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/1203 ,  H01L29/945

Abstract: An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.

Abstract translation: 一种集成电路，包括N +型层，设置在N +型层上的缓冲层; 形成在缓冲层上的P型区域; 覆盖N +型层的绝缘体层，覆盖绝缘体层的硅层，形成在硅层中并与延伸到N +型层的沟槽电容器的导电节点连接的嵌入式RAM FET，N +型层形成 沟槽电容器的平板电极，通过硅层和绝缘层的第一接触并且电连接到N +型层，形成在P型区域上方的硅层中的第一逻辑RAM FET，P型区域用作 第一逻辑RAM FET的P型背栅，以及通过硅层和绝缘层的第二接触，并且电连接到P型区域。