公开(公告)号：US06576943B1

公开(公告)日：2003-06-10

申请号：US09512827

申请日：2000-02-25

申请人： Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

发明人： Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

IPC分类号： H01L27108

CPC分类号： G11C16/0433 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10873 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/78642

摘要： A very thin semiconductor film is used for channels of semiconductor memory elements such that leak currents are reduced by the quantum-mechanical containment effect in the direction of film thickness. The amount of electrical charge accumulated in each charge accumulating region is used to change the conductance between a source region and a drain region of each read transistor structure. This conductance change is utilized for data storage. The thickness of the channel of the write transistor structure is preferably no more than 5 nm. According to one embodiment, the channel of the write transistor is formed by a semiconductor film deposited on a surface intersecting a principal plane of the substrate.

摘要翻译： 非常薄的半导体膜用于半导体存储元件的通道，使得漏电流通过膜厚度方向的量子力学容纳效应而降低。 使用在每个电荷累积区域中累积的电荷量来改变每个读取的晶体管结构的源极区域和漏极区域之间的电导。 该电导变化用于数据存储。 写入晶体管结构的沟道的厚度优选不大于5nm。 根据一个实施例，写入晶体管的沟道由沉积在与衬底的主平面相交的表面上的半导体膜形成。

公开(公告)号：US06291852B1

公开(公告)日：2001-09-18

申请号：US09521970

申请日：2000-03-09

申请人： Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

发明人： Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

IPC分类号： H01L2976

CPC分类号： B82Y10/00 ,  G11C11/22 ,  G11C11/404 ,  G11C16/02 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/28 ,  G11C2216/06 ,  G11C2216/08 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11551 ,  H01L27/1203 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7613 ,  H01L29/785 ,  H01L29/7888

摘要： A field-effect semiconductor element implemented with a reduced number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature. In accordance with one embodiment, a carrier confinement region, isolated from a channel and a gate of the semiconductor FET element, is provided to operate as a storage node for trapping the carrier or carriers.

摘要翻译： 一种场效应半导体元件，其具有减少的元件数量和减少的面积，并且能够自身存储数据，而不需要在低温下进行冷却;以及采用该半导体元件的存储器件。 栅极沟道电容被设置得如此小，以致捕获捕获一个电子或空穴是否可以根据半导体FET元件的电流的变化来明确且明显地被检测。 通过检测通过在陷阱中捕获电子或空穴而导致的半导体元件的阈值电压的变化，可以在室温下实现数据存储。 根据一个实施例，提供了从沟道隔离的载流子限制区域和半导体FET元件的栅极，以用作捕获载体或载流子的存储节点。

公开(公告)号：US6135577A

公开(公告)日：2000-10-24

申请号：US103938

申请日：1998-06-25

申请人： Tomoyuki Ishii

发明人： Tomoyuki Ishii

IPC分类号： B60T17/22 ,  B60T8/40 ,  B60T13/14 ,  F04B49/06 ,  B06T8/44

CPC分类号： B60T13/14 ,  B60T8/4045 ,  F04B49/065 ,  F04B2203/0201 ,  F04B2203/0202 ,  F04B2203/0213 ,  F04B2205/064 ,  F04B2205/07 ,  F04B2205/13 ,  F04B2207/043

摘要： In a pump operation control apparatus for a hydraulic brake boosting system, an ECU 13 is provided with a timer 16 to which an output signal from a brake switch 12 is supplied and a pump-operation-control-signal generating means 17 for transmitting a signal for operating and controlling a motor 9 in response to an output signal from the timer 16. When the brake switch 12 has been switched on, the operation of the pump is started. After predetermined time T has elapsed from a moment at which the brake switch 12 has been switched on, the operation of the pump is interrupted. If the brake switch 12 is continuously switched on after the predetermined time T has elapsed, the pump is operated for time elongated from the predetermined time T until the brake switch 12 is switched off. If the brake switch 12 is again switched on before the predetermined time T elapses, the pump is operated until the predetermined time T elapses from the moment at which the brake switch 12 has again been switched on.

摘要翻译： 在液压制动器升压系统的泵运转控制装置中，ECU13具有：来自制动开关12的输出信号的定时器16;以及用于发送信号的泵运转控制信号生成单元17 用于响应于来自定时器16的输出信号来操作和控制电动机9.当制动开关12接通时，泵的操作开始。 在从制动开关12接通的时刻经过了预定时间T之后，泵的操作被中断。 如果在经过预定时间T之后制动开关12连续接通，则泵从预定时间T延长到制动开关12关闭的时间。 如果制动开关12在经过预定时间T之前再次接通，则泵将被操作直到从制动开关12再次接通的时刻经过预定时间T。

公开(公告)号：US5444622A

公开(公告)日：1995-08-22

申请号：US220455

申请日：1994-03-30

申请人： Sadao Takeshima ,  Tomoyuki Ishii

发明人： Sadao Takeshima ,  Tomoyuki Ishii

IPC分类号： B62D6/02 ,  B62D5/04

CPC分类号： B62D5/0466

摘要： In a method of controlling an electric power steering apparatus by controlling a drive force of a steering force assisting electric motor when a vehicle speed is lower than a predetermined speed and controlling a braking force of the electric motor when the vehicle speed exceeds the predetermined speed, a steering wheel forward or reverse turning state is determined in accordance with a change in steering torque when the vehicle speed exceeds the predetermined state. The braking force of the electric motor is controlled only when the steering wheel reverse turning state is detected.

摘要翻译： 在车速低于预定速度时通过控制转向力辅助电动机的驱动力来控制电动转向装置的方法，并且当车速超过预定速度时控制电动机的制动力， 当车速超过预定状态时，根据转向转矩的变化来确定方向盘正向或反转状态。 仅当检测到方向盘反向转动状态时才控制电动机的制动力。

公开(公告)号：US20110252336A1

公开(公告)日：2011-10-13

申请号：US13125704

申请日：2008-10-22

申请人： Tomoyuki Ishii ,  Keiichi Sato

发明人： Tomoyuki Ishii ,  Keiichi Sato

IPC分类号： G06F3/01

CPC分类号： G16H40/20 ,  G16H10/60

摘要： A management information visualization device (management provider server 30) according to the present invention includes: an information registration management unit (information management unit 304) that registers service information transmitted from a service providing device (service provider server 20), associating the service information with user identification information and service content identification information which are related to the service information; and an information input/output unit (user GUI providing unit 303) that receives, from a user device, a request for viewing service information, creates management information (a top screen) including a service content list associated with service content identification information and transmits the management information to the user device, and, when one of the service content list displayed on the user device being selected by operation, searches in a management information DB300 and transmits corresponding service information to the user device.

摘要翻译： 根据本发明的管理信息可视化设备（管理提供商服务器30）包括：信息注册管理单元（信息管理单元304），其注册从服务提供设备（服务提供商服务器20）发送的服务信息，将服务信息 具有与服务信息相关的用户识别信息和服务内容识别信息; 以及信息输入/输出单元（用户GUI提供单元303），其从用户设备接收对查看服务信息的请求，创建包括与服务内容识别信息相关联的服务内容列表的管理信息（顶层屏幕）并发送 管理信息到用户装置，当通过操作选择显示在用户装置上的服务内容列表中的一个在管理信息DB300中进行搜索并将相应的服务信息发送到用户装置时。

公开(公告)号：US20110169070A1

公开(公告)日：2011-07-14

申请号：US13072211

申请日：2011-03-25

申请人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

发明人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

IPC分类号： H01L27/088

CPC分类号： H01L27/11521 ,  B82Y10/00 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/06 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7887

摘要： For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.

摘要翻译： 为了通过电池级提供具有提高可靠性的便宜的半导体存储器件，以代替通过诸如ECC的电存储器单元中的缺陷脱离，并且还用于提供能够在垂直方向上按比例缩小的单元结构，同时保持 在需要高速读出操作的半导体存储器件中的可靠性，电荷存储区域由大量半导体电荷存储小区域制成的粒子构成，各自独立，从而通过 细胞水平。

公开(公告)号：US07622766B2

公开(公告)日：2009-11-24

申请号：US11808228

申请日：2007-06-07

申请人： Tomoyuki Ishii ,  Taro Osabe ,  Hideaki Kurata ,  Takeshi Sakata

发明人： Tomoyuki Ishii ,  Taro Osabe ,  Hideaki Kurata ,  Takeshi Sakata

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  B82Y10/00 ,  G11C11/5621 ,  G11C11/5671 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0475 ,  G11C16/0491 ,  G11C2216/06 ,  H01L27/115 ,  H01L27/11521

摘要： Disclosed is a non-volatile semiconductor memory device that uses a inversion layer provided on a semiconductor substrate as a data line. The memory device can reduce variation of characteristics among memory cells and can reduce bit cost. A plurality of assist gates are formed in the upper part of a p-type well through a gate oxide film. In the upper part of an interlayer insulator that covers those assist gates are formed word lines that are used as control electrodes. The width of those word lines is, for example, 0.1 μm, and each word line is separated from its adjacent word lines by a side wall spacer that is a silicon oxide film having a thickness of about 20 nm.

摘要翻译： 公开了使用设置在半导体衬底上的反转层作为数据线的非易失性半导体存储器件。 存储器件可以减少存储器单元之间的特性变化并且可以降低位成本。 多个辅助栅极通过栅极氧化膜形成在p型阱的上部。 在覆盖这些辅助栅极的层间绝缘体的上部形成用作控制电极的字线。 这些字线的宽度例如为0.1μm，并且每个字线通过作为厚度为约20nm的氧化硅膜的侧壁间隔物与其相邻字线分开。

公开(公告)号：US20090237685A1

公开(公告)日：2009-09-24

申请号：US12381313

申请日：2009-03-10

申请人： Takeshi Nishihara ,  Yozo Ohki ,  Tatsuji Goma ,  Tomoyuki Ishii ,  Takuya Yamamoto

发明人： Takeshi Nishihara ,  Yozo Ohki ,  Tatsuji Goma ,  Tomoyuki Ishii ,  Takuya Yamamoto

IPC分类号： H04N1/60 ,  B41J2/435

CPC分类号： G03G15/5062 ,  G03G2215/00063 ,  G03G2215/00067 ,  G03G2215/0164

摘要： A method of gradation correction for laser scanning exposure is effected, based on measured density values of a test print (TP) including a horizontal stripe test pattern comprised of a plurality of horizontal lines extending in the main scanning direction and a vertical stripe pattern comprised of a plurality of vertical lines extending in the sub scanning direction. The includes the steps of calculating, based on the measured density values, a rising correction amount for main scanning rising correction of adding a rising correction component to one dot after rising of a modulated laser in order to reduce density difference between the horizontal line and the vertical line and calculating, based on the measured density values, a falling correction amount for main scanning falling correction of adding a falling correction component to one dot after rising of the modulated laser in order to reduce the density difference between the horizontal line and the vertical line.

摘要翻译： 基于包括由在主扫描方向上延伸的多条水平线组成的水平条纹测试图案的测试印刷（TP）的测量密度值和由主扫描方向延伸的垂直条纹图案，实现激光扫描曝光的灰度校正方法 沿副扫描方向延伸的多条垂直线。 包括以下步骤：基于所测量的浓度值，计算用于在调制激光器升高之后将上升校正分量加到一个点上的主扫描上升校正的上升校正量，以便减小水平线和 垂直线，并且基于测量的浓度值，计算用于在调制激光器升高之后将下降校正分量加到下降校正分量的主扫描下降校正的下降校正量，以便降低水平线和垂直线之间的密度差 线。

公开(公告)号：US07468901B2

公开(公告)日：2008-12-23

申请号：US11399397

申请日：2006-04-07

申请人： Norifumi Kameshiro ,  Riichiro Takemura ,  Tomoyuki Ishii

发明人： Norifumi Kameshiro ,  Riichiro Takemura ,  Tomoyuki Ishii

IPC分类号： G11C7/00

CPC分类号： G11C11/405 ,  G11C7/18 ,  G11C11/4097 ,  G11C2211/4013 ,  H01L27/0207 ,  H01L27/108

摘要： In a two-transistor gain cell structure, a semiconductor memory device capable of stable reading without malfunction and having small-area memory cells is provided. In a two-transistor gain cell memory having a write transistor and a read transistor, a write word line, a read word line, a write bit line, and a read bit line are separately provided, and voltages to be applied are independently set. Furthermore, a memory cell is connected to the same read word line and write bit line as those of an adjacent memory cell.

摘要翻译： 在双晶体管增益单元结构中，提供了能够稳定读取而没有故障并且具有小面积存储单元的半导体存储器件。 在具有写晶体管和读晶体管的双晶体管增益单元存储器中，分别提供写字线，读字线，写位线和读位线，并且独立地设置要施加的电压。 此外，存储单元连接到与相邻存储单元相同的读字线和写位线。

公开(公告)号：US07375399B2

公开(公告)日：2008-05-20

申请号：US11156558

申请日：2005-06-21

申请人： Tomoyuki Ishii ,  Toshiyuki Mine ,  Toshiaki Sano ,  Norifumi Kameshiro

发明人： Tomoyuki Ishii ,  Toshiyuki Mine ,  Toshiaki Sano ,  Norifumi Kameshiro

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L27/105 ,  G11C11/405 ,  G11C2207/104 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1116

摘要： The present invention is a semiconductor memory device having a logic block and a memory block on the same chip. In the memory device, unit memory cells each include at least two transistors, one of which is a write transistor for storing an electric charge into and releasing it from an electric charge storage node, and the other is a read transistor whose conductance in a channel region provided between a source and drain of the read transistor is modulated dependently on the amount of electric charge stored into or released from the electric charge storage node by the write transistor. The read transistor has a gate-insulating film thicker than that of a transistor provided in the logic block, and uses the same diffusion layer structure as that of the logic block.

摘要翻译： 本发明是具有在同一芯片上的逻辑块和存储器块的半导体存储器件。 在存储器件中，单元存储单元每个都包括至少两个晶体管，其中之一是用于存储电荷并将其从电荷存储节点释放的写入晶体管，另一个是在沟道中的电导 读取晶体管的源极和漏极之间的区域被调制，取决于由写入晶体管存储或从电荷存储节点释放的电荷的量。 读取晶体管具有比设置在逻辑块中的晶体管更厚的栅极绝缘膜，并且使用与逻辑块相同的扩散层结构。