公开(公告)号：US09263342B2

公开(公告)日：2016-02-16

申请号：US13411214

申请日：2012-03-02

Applicant: Tsung-Lin Lee ,  Feng Yuan ,  Hung-Li Chiang ,  Chih Chieh Yeh

Inventor： Tsung-Lin Lee ,  Feng Yuan ,  Hung-Li Chiang ,  Chih Chieh Yeh

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/66803 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: The present disclosure provides devices and methods which provide for strained epitaxial regions. A method of semiconductor fabrication is provided that includes forming a gate structure over a fin of a semiconductor substrate and forming a recess in the fin adjacent the gate structure. A sidewall of the recess is then altered. Exemplary alterations include having an altered profile, treating the sidewall, and forming a layer on the sidewall. An epitaxial region is then grown in the recess. The epitaxial region interfaces the altered sidewall of the recess and is a strained epitaxial region.

Abstract translation: 本公开提供了提供应变外延区域的装置和方法。 提供一种半导体制造方法，其包括在半导体衬底的翅片上形成栅极结构，并在靠近栅极结构的鳍中形成凹陷。 然后改变凹槽的侧壁。 示例性改变包括具有改变的轮廓，处理侧壁以及在侧壁上形成层。 然后在凹槽中生长外延区域。 外延区域与凹陷的改变的侧壁接触并且是应变的外延区域。

公开(公告)号：US08653608B2

公开(公告)日：2014-02-18

申请号：US12842281

申请日：2010-07-23

Applicant: Tsung-Lin Lee ,  Chih Chieh Yeh

Inventor： Tsung-Lin Lee ,  Chih Chieh Yeh

IPC: H01L27/088

CPC classification number: H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L2029/7858

Abstract: An integrated circuit structure includes a substrate and a fin field-effect transistor (FinFET). The FinFET includes a fin over the substrate and having a first fin portion and a second fin portion. A gate stack is formed on a top surface and sidewalls of the first fin portion. An epitaxial semiconductor layer has a first portion formed directly over the second fin portion, and a second portion formed on sidewalls of the second fin portion. A silicide layer is formed on the epitaxial semiconductor layer. A peripheral ratio of a total length of an effective silicide peripheral of the FinFET to a total length of a fin peripheral of the FinFET is greater than 1.

Abstract translation: 集成电路结构包括衬底和鳍状场效应晶体管（FinFET）。 FinFET在衬底上包括翅片，并具有第一鳍片部分和第二鳍片部分。 栅堆叠形成在第一鳍部的顶表面和侧壁上。 外延半导体层具有直接形成在第二鳍部上的第一部分和形成在第二鳍部的侧壁上的第二部分。 在外延半导体层上形成硅化物层。 FinFET的有效硅化物周边的总长度与FinFET的鳍状外围的总长度的周长比大于1。

公开(公告)号：US08507996B2

公开(公告)日：2013-08-13

申请号：US12789046

申请日：2010-05-27

Applicant: Sey-Ping Sun ,  Chih-Hao Chang ,  Chao-An Jong ,  Tsung-Lin Lee ,  Chung-Ju Lee ,  Chin-Hsiang Lin

Inventor： Sey-Ping Sun ,  Chih-Hao Chang ,  Chao-An Jong ,  Tsung-Lin Lee ,  Chung-Ju Lee ,  Chin-Hsiang Lin

IPC: H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/76804 ,  H01L21/76816 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure includes a semiconductor substrate; a gate stack overlying the semiconductor substrate; a gate spacer on a sidewall of the gate stack; a first contact plug having an inner edge contacting a sidewall of the gate spacer, and a top surface level with a top surface of the gate stack; and a second contact plug over and contacting the first contact plug. The second contact plug has a cross-sectional area smaller than a cross-sectional area of the first contact plug.

Abstract translation: 集成电路结构包括半导体衬底; 覆盖半导体衬底的栅极堆叠; 在栅极堆叠的侧壁上的栅极间隔物; 具有接触所述栅极隔离物的侧壁的内边缘的第一接触插塞和具有所述栅极堆叠的顶表面的顶表面水平; 以及第二接触插头，并且与第一接触插塞接触。 第二接触插塞的横截面积小于第一接触插塞的横截面面积。

公开(公告)号：US20110117679A1

公开(公告)日：2011-05-19

申请号：US12622038

申请日：2009-11-19

Applicant: Tsung-Lin Lee ,  Feng Yuan ,  Chih Chieh Yeh

Inventor： Tsung-Lin Lee ,  Feng Yuan ,  Chih Chieh Yeh

IPC: H01L21/66 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary embodiment of the method includes providing a substrate; forming a fin structure over the substrate; forming a gate structure, wherein the gate structure overlies a portion of the fin structure; forming a sacrificial-offset-protection layer over another portion of the fin structure; and thereafter performing an implantation process.

Abstract translation: 公开了一种制造半导体器件的方法。 该方法的示例性实施例包括提供衬底; 在衬底上形成翅片结构; 形成栅极结构，其中所述栅极结构覆盖所述翅片结构的一部分; 在翅片结构的另一部分上形成牺牲偏移保护层; 然后进行植入处理。

公开(公告)号：US07482231B2

公开(公告)日：2009-01-27

申请号：US11529067

申请日：2006-09-28

Applicant: Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

Inventor： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

IPC: H01L21/8239

CPC classification number: H01L29/4983 ,  H01L21/28282 ,  H01L21/823828 ,  H01L21/823864 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

Abstract: Method of manufacturing a semiconductor chip. An array region gate stack is formed on an array region of a substrate and a periphery region gate stack is formed on a periphery region of a substrate. A first dielectric material, a charge-storing material, and a second dielectric material are deposited over the substrate. Portions of the first dielectric material, the charge-storing material, and the second dielectric material are removed to form storage structures on the array region gate stack and on the periphery region gate stack. The storage structures have a generally L-shaped cross-section. A first source/drain region is formed in the array region well. A third dielectric material and a spacer material are deposited over the substrate. Portions of the third dielectric material and the spacer material are removed to form spacers. A second source/drain region is formed in the periphery region well.

Abstract translation: 制造半导体芯片的方法 在基板的阵列区域上形成阵列区域栅极叠层，并且在基板的周边区域上形成周边区域栅叠层。 在衬底上沉积第一介电材料，电荷存储材料和第二介电材料。 去除第一介电材料的部分，电荷存储材料和第二介电材料，以在阵列区域栅极叠层和周边区域栅叠层上形成存储结构。 存储结构具有大致L形的横截面。 在阵列区域中形成第一源极/漏极区域。 在衬底上沉积第三介电材料和间隔物材料。 去除第三电介质材料和间隔物材料的部分以形成间隔物。 在周边区域中形成第二源极/漏极区域。

公开(公告)号：US20070268747A1

公开(公告)日：2007-11-22

申请号：US11483819

申请日：2006-07-10

Applicant: Wesley Lin ,  Fang-Shi Jordan Lai ,  Chia-Fu Lee ,  Sheng Chi Lin ,  Ping-Wei Wang ,  Chang-Yun Chang ,  Tang-Xuan Zhong ,  Tsung-Lin Lee

Inventor： Wesley Lin ,  Fang-Shi Jordan Lai ,  Chia-Fu Lee ,  Sheng Chi Lin ,  Ping-Wei Wang ,  Chang-Yun Chang ,  Tang-Xuan Zhong ,  Tsung-Lin Lee

IPC: G11C11/34

CPC classification number: G11C11/4125

Abstract: A static random access memory (SRAM) cell includes a first load device, a first pull-down transistor, and a switch-box coupled between the first load device and the first pull-down transistor. The switch-box is configured to receive a switch control signal to turn off a first connection between the first load device and the first pull-down transistor during read operations of the SRAM cell and to turn on the first connection during write operations.

Abstract translation: 静态随机存取存储器（SRAM）单元包括耦合在第一负载器件和第一下拉晶体管之间的第一负载器件，第一下拉晶体管和开关盒。 开关盒被配置为在SRAM单元的读取操作期间接收开关控制信号以关闭第一负载装置和第一下拉晶体管之间的第一连接，并且在写入操作期间接通第一连接。

公开(公告)号：US20070075385A1

公开(公告)日：2007-04-05

申请号：US11243165

申请日：2005-10-04

Applicant: Tzyh-Cheang Lee ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

Inventor： Tzyh-Cheang Lee ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

IPC: H01L29/94 ,  H01L29/76

CPC classification number: H01L29/7923 ,  H01L29/40117 ,  H01L29/4234

Abstract: A SONOS gate structure has an oxide structure on a substrate having gate pattern thereon. The oxide structure has a relatively thinner oxide portion on the substrate for keeping good program/erase efficiency, and a relatively thicker oxide portion on sidewalls of the gate pattern for inhibiting gate disturb. Trapping dielectric spacers are on formed the oxide structure laterally adjacent to said sidewalls of said gate pattern respectively.

Abstract translation: SONOS栅极结构在其上具有栅极图案的衬底上具有氧化物结构。 氧化物结构在衬底上具有相对较薄的氧化物部分，用于保持良好的编程/擦除效率，并且在用于抑制栅极干扰的栅极图案的侧壁上的相对较厚的氧化物部分。 捕获电介质间隔物分别形成在与所述栅极图案的所述侧壁相邻的氧化物结构上。

公开(公告)号：US09171929B2

公开(公告)日：2015-10-27

申请号：US13487860

申请日：2012-06-04

Applicant: Tsung-Lin Lee ,  Chih Chieh Yeh ,  Feng Yuan ,  Cheng-Yi Peng ,  Clement Hsingjen Wann

Inventor： Tsung-Lin Lee ,  Chih Chieh Yeh ,  Feng Yuan ,  Cheng-Yi Peng ,  Clement Hsingjen Wann

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/02

CPC classification number: H01L29/66636 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/0262 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66651 ,  H01L29/7848

Abstract: An exemplary structure for a field effect transistor (FET) comprises a silicon substrate comprising a first surface; a channel portion over the first surface, wherein the channel portion has a second surface at a first height above the first surface, and a length parallel to first surface; and two source/drain (S/D) regions on the first surface and surrounding the channel portion along the length of the channel portion, wherein the two S/D regions comprise SiGe, Ge, Si, SiC, GeSn, SiGeSn, SiSn, or III-V material.

Abstract translation: 用于场效应晶体管（FET）的示例性结构包括：硅衬底，其包括第一表面; 在所述第一表面上的通道部分，其中所述通道部分具有​​在所述第一表面上方的第一高度处的第二表面和平行于第一表面的长度; 以及沿沟道部分的长度围绕沟道部分的两个源极/漏极（S / D）区域，其中两个S / D区域包括SiGe，Ge，Si，SiC，GeSn，SiGeSn，SiSn， 或III-V材料。

公开(公告)号：US20130228862A1

公开(公告)日：2013-09-05

申请号：US13411214

申请日：2012-03-02

Applicant: Tsung-Lin Lee ,  Feng Yuan ,  Hung-Li Chiang ,  Chih Chieh Yeh

Inventor： Tsung-Lin Lee ,  Feng Yuan ,  Hung-Li Chiang ,  Chih Chieh Yeh

IPC: H01L27/12 ,  H01L21/336 ,  H01L21/20

CPC classification number: H01L29/66803 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: The present disclosure provides devices and methods which provide for strained epitaxial regions. A method of semiconductor fabrication is provided that includes forming a gate structure over a fin of a semiconductor substrate and forming a recess in the fin adjacent the gate structure. A sidewall of the recess is then altered. Exemplary alterations include having an altered profile, treating the sidewall, and forming a layer on the sidewall. An epitaxial region is then grown in the recess. The epitaxial region interfaces the altered sidewall of the recess and is a strained epitaxial region.

Abstract translation: 本公开提供了提供应变外延区域的装置和方法。 提供一种半导体制造方法，其包括在半导体衬底的翅片上形成栅极结构，并在与栅极结构相邻的鳍中形成凹陷。 然后改变凹槽的侧壁。 示例性改变包括具有改变的轮廓，处理侧壁以及在侧壁上形成层。 然后在凹槽中生长外延区域。 外延区域与凹陷的改变的侧壁接触并且是应变的外延区域。

公开(公告)号：US08497528B2

公开(公告)日：2013-07-30

申请号：US12775006

申请日：2010-05-06

Applicant: Tsung-Lin Lee ,  Chih-Hao Chang ,  Chih-Hsin Ko ,  Feng Yuan ,  Jeff J. Xu

Inventor： Tsung-Lin Lee ,  Chih-Hao Chang ,  Chih-Hsin Ko ,  Feng Yuan ,  Jeff J. Xu

IPC: H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/76 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0856 ,  H01L29/0873 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A structure for a field effect transistor on a substrate that includes a gate stack, an isolation structure and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the gate stack and the isolation structure. The recess cavity having a lower portion and an upper portion. The lower portion having a first strained layer and a first dielectric film. The first strained layer disposed between the isolation structure and the first dielectric film. A thickness of the first dielectric film less than a thickness of the first strained layer. The upper portion having a second strained layer overlying the first strained layer and first dielectric film.

Abstract translation: 一种用于衬底上的场效应晶体管的结构，其包括栅极堆叠，隔离结构以及位于栅叠层和隔离结构之间的衬底顶表面下方的源极/漏极（S / D）凹槽。 该凹腔具有下部和上部。 下部具有第一应变层和第一介电膜。 第一应变层设置在隔离结构和第一介电膜之间。 第一电介质膜的厚度小于第一应变层的厚度。 上部具有覆盖在第一应变层和第一介电膜上的第二应变层。