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    Semiconductor device capable of controlling OCD and ODT circuits and control method used by the semiconductor device
    21.
    发明申请
    Semiconductor device capable of controlling OCD and ODT circuits and control method used by the semiconductor device 有权
    能够控制OCD和ODT电路的半导体器件和半导体器件使用的控制方法

    公开(公告)号：US20060226868A1

    公开(公告)日：2006-10-12

    申请号：US11402123

    申请日：2006-04-11

    Applicant: Woo-Jin Lee ,  Kwang-Il Park ,  Hyun-Jin Kim ,  Seong-Jin Jang

    Inventor： Woo-Jin Lee ,  Kwang-Il Park ,  Hyun-Jin Kim ,  Seong-Jin Jang

    IPC: H03K19/003

    CPC classification number: H03K19/0005

    Abstract: Provided is a semiconductor device capable of controlling an on-die-termination (ODT) circuit and an off-chip-driver (OCD) circuit and a control method used by the semiconductor device. The semiconductor device includes a control code generation unit generating a control code in response to a control signal, an addition unit adding an adjustment code to the control code to produce an adjusted control code, and an ODT circuit, wherein an impedance of the ODT circuit is adjusted in response to the adjusted control code. The semiconductor device can adjust the control code more precisely by adding or subtracting the adjustment code to or from the control code. Accordingly, the impedance of an OCD circuit or ODT circuit can be adjusted more precisely.

    Abstract translation: 提供了能够控制芯片上终端（ODT）电路和芯片外驱动器（OCD）电路的半导体器件以及由半导体器件使用的控制方法。 半导体器件包括响应于控制信号产生控制代码的控制代码生成单元，向控制代码添加调整代码以产生调整后的控制代码的加法单元和ODT电路，其中ODT电路的阻抗 根据调整后的控制代码进行调整。 半导体器件可以通过向或从控制代码添加或减去调整代码来更精确地调整控制代码。 因此，可以更精确地调整OCD电路或ODT电路的阻抗。

    Input buffer having a stabilized operating point and an associated method
    22.
    发明申请
    Input buffer having a stabilized operating point and an associated method 失效
    输入缓冲器具有稳定的工作点和相关联的方法

    公开(公告)号：US20060066364A1

    公开(公告)日：2006-03-30

    申请号：US11225915

    申请日：2005-09-13

    Applicant: Hyun-Jin Kim ,  Seong-Jin Jang ,  Kwang-Il Park ,  Sang-Joon Hwang ,  Ho-Young Song ,  Ho-Kyong Lee ,  Woo-Jin Lee

    Inventor： Hyun-Jin Kim ,  Seong-Jin Jang ,  Kwang-Il Park ,  Sang-Joon Hwang ,  Ho-Young Song ,  Ho-Kyong Lee ,  Woo-Jin Lee

    IPC: H03B1/00

    CPC classification number: H03F3/45

    Abstract: We describe an input buffer having a stabilized operating point and an associated method. An input buffer may include a first differential amplifying unit to generate a first output signal having a first operating point and a second differential amplifying unit to generate a second output signal having a second operating point. An output control circuit varies respective weights of the first and second output signals responsive to an output control signal. The first differential amplifying unit may operate responsive to a reference voltage and an input voltage signal. The second differential amplifying unit may operate responsive to the reference voltage and the input voltage signal. The first operating point may be relatively higher than the second operating point.

    Abstract translation: 我们描述具有稳定的工作点和相关方法的输入缓冲器。 输入缓冲器可以包括：第一差分放大单元，用于产生具有第一工作点的第一输出信号和第二差分放大单元，以产生具有第二工作点的第二输出信号。 响应于输出控制信号，输出控制电路改变第一和第二输出信号的各个权重。 第一差分放大单元可以响应于参考电压和输入电压信号而进行操作。 第二差分放大单元可以响应于参考电压和输入电压信号而工作。 第一工作点可以相对高于第二工作点。

    Method for preparing anode electrode for high voltage electrolytic capacitor
    23.
    发明授权
    Method for preparing anode electrode for high voltage electrolytic capacitor 失效
    高压电解电容器阳极电极制作方法

    公开(公告)号：US06440288B1

    公开(公告)日：2002-08-27

    申请号：US09691153

    申请日：2000-10-19

    Applicant: Su Il Pyun ,  Woo Jin Lee

    Inventor： Su Il Pyun ,  Woo Jin Lee

    IPC: C25D1112

    CPC classification number: H01G9/0032 ,  Y10S205/917

    Abstract: Disclosed is a method for forming an aluminum oxide film of a large surface area on an electrode for a high voltage electrolytic capacitor. In accordance with the method, an oxide film of a uniform thickness is formed, prior to a process of etching the oxide film. A re-anodization is then partially conducted for an etched portion of the oxide film. The resultant oxide film has an increased surface area. The method of the invention makes it possible to prepare a dielectric oxide film having characteristics of a uniform thickness and a large surface area. In accordance with the invention, it is possible to expect an increase in the capacitance of electrolytic capacitors.

    Abstract translation: 公开了一种在高压电解电容器用电极上形成表面积大的氧化铝膜的方法。 根据该方法，在蚀刻氧化膜的过程之前，形成均匀厚度的氧化物膜。 然后对氧化膜的蚀刻部分部分地进行再阳极氧化。 所得氧化膜的表面积增加。 本发明的方法可以制备具有均匀厚度和大表面积特性的电介质氧化膜。 根据本发明，可以预期电解电容器的电容增加。

    SYSTEM ON CHIP METHOD THEREOF, AND DEVICE INCLUDING THE SAME
    26.
    发明申请
    SYSTEM ON CHIP METHOD THEREOF, AND DEVICE INCLUDING THE SAME 有权
    其芯片方法系统，以及包括其的装置

    公开(公告)号：US20150277534A1

    公开(公告)日：2015-10-01

    申请号：US14630015

    申请日：2015-02-24

    Applicant: Jong Lae Park ,  Woo Jin Lee ,  Sang IL Park ,  Gyeong Teak Lee

    Inventor： Jong Lae Park ,  Woo Jin Lee ,  Sang IL Park ,  Gyeong Teak Lee

    IPC: G06F1/32

    CPC classification number: G06F1/329 ,  G06F1/163 ,  G06F1/3206 ,  G06F1/3296 ,  Y02D10/172 ,  Y02D10/24

    Abstract: A Dynamic Voltage and Frequency Scaling (DVFS) method, comprising of a scheduling execution of DVFS to adjust frequency or voltage of a target device at a first scheduled time; monitoring operating frequency of the target device; and selectively deferring execution of DVFS at a later scheduled time based on the operating frequency of the target device; wherein execution of DVFS at a next scheduled time is deferred when the operating frequency of the target device is below a given minimum frequency.

    Abstract translation: 一种动态电压和频率缩放（DVFS）方法，包括：调度执行DVFS以在第一预定时间调整目标设备的频率或电压; 监控目标设备的工作频率; 并且基于目标设备的操作频率选择性地推迟在稍后的安排时间执行DVFS; 其中当目标设备的操作频率低于给定的最小频率时，下一个调度时间的DVFS的执行被延迟。

    SEMICONDUCTOR MEMORY DEVICE AND SYSTEM HAVING REDUNDANCY CELLS
    30.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND SYSTEM HAVING REDUNDANCY CELLS 审中-公开
    具有冗余电池的半导体存储器件和系统

    公开(公告)号：US20130117636A1

    公开(公告)日：2013-05-09

    申请号：US13670822

    申请日：2012-11-07

    Applicant: Su-a KIM ,  Dae-hyun KIM ,  Woo-jin LEE

    Inventor： Su-a KIM ,  Dae-hyun KIM ,  Woo-jin LEE

    IPC: G11C29/04 ,  G06F11/16

    CPC classification number: G11C29/04 ,  G11C7/1045 ,  G11C29/808 ,  G11C29/81 ,  G11C29/848

    Abstract: In one embodiment, the memory device includes a memory cell array, a data line selection circuit and selection control logic. The memory cell array has at least a first memory cell group and a redundancy memory cell group. The first memory cell group includes a plurality of first memory cells associated with a first data line, and the redundancy memory cell group includes a plurality of redundancy memory cells associated with a redundancy data line. The selection control logic is configured to detect if a defective memory cell in the first memory cell group is being accessed, and is configured to control the data line selection circuit to replace access via the first data line with access via the redundancy data line such that a detected defective memory cell in the first memory cell group is replaced with one of the plurality of redundancy memory cells.

    Abstract translation: 在一个实施例中，存储器件包括存储单元阵列，数据线选择电路和选择控制逻辑。 存储单元阵列具有至少第一存储单元组和冗余存储单元组。 第一存储单元组包括与第一数据线相关联的多个第一存储单元，并且冗余存储单元组包括与冗余数据线相关联的多个冗余存储单元。 所述选择控制逻辑被配置为检测所述第一存储器单元组中的有缺陷的存储单元是否被访问，并且被配置为控制所述数据线选择电路经由所述冗余数据线经由所述第一数据线的访问来替换访问，使得 第一存储单元组中的检测到的有缺陷的存储单元被多个冗余存储单元中的一个代替。

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