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    Bag with anti-theft function cross reference to related application
    1.
    发明授权
    Bag with anti-theft function cross reference to related application 有权
    手提袋具有防盗功​​能，交叉参考相关应用

    公开(公告)号：US09345300B2

    公开(公告)日：2016-05-24

    申请号：US14297560

    申请日：2014-06-05

    申请人： Sang Il Park

    发明人： Sang Il Park

    IPC分类号： G08B13/14 ,  A45C13/18

    CPC分类号： A45C13/18 ,  A45C13/20 ,  E05B65/52 ,  E05B73/0005 ,  G08B13/14 ,  G08B13/149

    摘要： Disclosed herein is a bag with an anti-theft function which is used to temporarily store various valuables (a wallet, a cellular phone, a camera, a watch, etc.) or clothes in a crowded place, for example, a water play area such as a beach or a water park, and is configured such that the stored valuables or the bag itself can be prevented from being stolen. The bag according to the present invention includes an anti-theft device which fastens first and second zippers that openably close an opening of the bag body to each other and binds the bag body to a surrounding structure, whereby valuables (a wallet, a cellular phone, a camera, a watch, etc.) stored in the bag body not only can be prevented from being stolen but the bag itself can also be prevented from being stolen because it is bound to the surrounding structure.

    摘要翻译： 本文公开了一种具有防盗功​​能的袋子，其用于临时存储各种贵重物品（钱包，手机，相机，手表等）或衣服在拥挤的地方，例如水上游乐区域 例如海滩或水上公园，并且被配置为使得可以防止存储的贵重物品或袋本身被盗。 根据本发明的袋子包括一个防盗装置，该防盗装置将第一和第二拉链紧固在一起，使第一和第二拉链可打开地将袋体的开口彼此靠近并将袋体绑在周围的结构上，由此贵重物品（钱包，蜂窝电话 ，相机，手表等）不仅可以防止被盗，而且还可以防止袋本身因为与周围结构的束缚而被盗。

    SYSTEM ON CHIP METHOD THEREOF, AND DEVICE INCLUDING THE SAME
    2.
    发明申请
    SYSTEM ON CHIP METHOD THEREOF, AND DEVICE INCLUDING THE SAME 有权
    其芯片方法系统，以及包括其的装置

    公开(公告)号：US20150277534A1

    公开(公告)日：2015-10-01

    申请号：US14630015

    申请日：2015-02-24

    申请人： Jong Lae Park ,  Woo Jin Lee ,  Sang IL Park ,  Gyeong Teak Lee

    发明人： Jong Lae Park ,  Woo Jin Lee ,  Sang IL Park ,  Gyeong Teak Lee

    IPC分类号： G06F1/32

    CPC分类号： G06F1/329 ,  G06F1/163 ,  G06F1/3206 ,  G06F1/3296 ,  Y02D10/172 ,  Y02D10/24

    摘要： A Dynamic Voltage and Frequency Scaling (DVFS) method, comprising of a scheduling execution of DVFS to adjust frequency or voltage of a target device at a first scheduled time; monitoring operating frequency of the target device; and selectively deferring execution of DVFS at a later scheduled time based on the operating frequency of the target device; wherein execution of DVFS at a next scheduled time is deferred when the operating frequency of the target device is below a given minimum frequency.

    摘要翻译： 一种动态电压和频率缩放（DVFS）方法，包括：调度执行DVFS以在第一预定时间调整目标设备的频率或电压; 监控目标设备的工作频率; 并且基于目标设备的操作频率选择性地推迟在稍后的安排时间执行DVFS; 其中当目标设备的操作频率低于给定的最小频率时，下一个调度时间的DVFS的执行被延迟。

    Semiconductor memory device and method for repairing the same
    6.
    发明授权
    Semiconductor memory device and method for repairing the same 有权
    半导体存储器件及其修复方法

    公开(公告)号：US08570821B2

    公开(公告)日：2013-10-29

    申请号：US13191625

    申请日：2011-07-27

    申请人： Sun Young Hwang ,  Sang Il Park

    发明人： Sun Young Hwang ,  Sang Il Park

    IPC分类号： G11C29/00

    CPC分类号： G11C29/4401 ,  G11C29/789

    摘要： A semiconductor memory device includes a latch address generation unit configured to latch row addresses to generate first and second latch addresses when at least one of memory cells coupled to sub word lines is faulty, wherein the first and second latch addresses select different main word lines, and a repair unit configured to perform a repair operation on memory cells coupled to the main word lines selected by the first and second latch addresses.

    摘要翻译： 半导体存储器件包括锁存地址生成单元，其被配置为当耦合到子字线的存储器单元中的至少一个有故障时，锁存行地址以产生第一和第二锁存器地址，其中第一和第二锁存器地址选择不同的主字线， 以及修复单元，被配置为对与由第一和第二锁存器地址选择的主字线耦合的存储器单元执行修复操作。

    Semiconductor memory device having a reduced noise interference
    8.
    发明授权
    Semiconductor memory device having a reduced noise interference 有权
    具有降低的噪声干扰的半导体存储器件

    公开(公告)号：US08279694B2

    公开(公告)日：2012-10-02

    申请号：US12826918

    申请日：2010-06-30

    申请人： Duck Hwa Hong ,  Sang Il Park

    发明人： Duck Hwa Hong ,  Sang Il Park

    IPC分类号： G11C16/04

    CPC分类号： G11C11/4091 ,  G11C7/02 ,  G11C7/06 ,  G11C7/08

    摘要： A semiconductor memory device having a reduced noise interference is presented. The semiconductor memory device includes a first switch and a second switch. The first switch is disposed in a sub hole region or an edge region and is configured to be turned on in response to a first pre-control signal, which is enabled before a time point at which a sense amplifier array begins to operate, and to apply an external voltage to a first voltage line through which a bias voltage is supplied to the sense amplifier array. The second switch is configured to be turned on in response to a first control signal, which is enabled in a sense amplifier overdriving period, and to apply the external voltage to the first voltage line.

    摘要翻译： 提出了具有降低的噪声干扰的半导体存储器件。 半导体存储器件包括第一开关和第二开关。 第一开关设置在子孔区域或边缘区域中，并且被配置为响应于在读出放大器阵列开始运行的时间点之前使能的第一预控制信号而导通，以及 将外部电压施加到向读出放大器阵列提供偏置电压的第一电压线。 第二开关被配置为响应于在感测放大器过驱动周期中被使能的第一控制信号而导通，并且将外部电压施加到第一电压线。

    REFRESH CIRCUIT
    9.
    发明申请
    REFRESH CIRCUIT 有权
    刷新电路

    公开(公告)号：US20120195150A1

    公开(公告)日：2012-08-02

    申请号：US13191687

    申请日：2011-07-27

    申请人： Sang Il PARK

    发明人： Sang Il PARK

    IPC分类号： G11C11/402

    CPC分类号： G11C11/40618 ,  G11C11/408

    摘要： A refresh circuit includes an enable pulse generator configured to generate a first enable pulse and a second enable pulse, a first address latch configured to latch the first row address in synchronization with the first enable pulse and generate a first latch address, and a second address latch configured to latch a second row address in synchronization with the second enable pulse and generate second and third latch addresses.

    摘要翻译： 刷新电路包括配置用于产生第一使能脉冲和第二使能脉冲的使能脉冲发生器，配置成与第一使能脉冲同步地锁存第一行地址并产生第一锁存器地址的第一地址锁存器，以及第二地址 锁存器被配置为与第二使能脉冲同步地锁存第二行地址并产生第二和第三锁存器地址。